Inventor

SAKUMA KATSUYUKI

US75 patents

⚠️ This page may combine multiple inventors who share the name “SAKUMA KATSUYUKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAKUMA KATSUYUKI

IBM

Liquid crystal display driver and method thereof

Liquid crystal display

Selective area heating for 3D chip stack

Selective area heating for 3D chip stack

Flexible electronics for wearable healthcare sensors

Selective area heating for 3D chip stack

Integrated circuit bonding with interposer die

Selective area heating for 3D chip stack

Underfill material dispensing for stacked semiconductor chips

Multiple die assembly

Solder transfer integrated circuit packaging

Circuit substrate with mixed pitch wiring

Structure and method for bridge chip assembly with capillary underfill

Strain gauge structure for a sensor

Eye-mounted hearing aid

Eye-mounted hearing aid

Eye-mounted hearing aid

Ball grid array and land grid array assemblies fabricated using temporary resist

Micro-scrub process for fluxless micro-bump bonding

Reduced volume interconnect for three-dimensional chip stack

Flexible electronics for wearable healthcare sensors

Reduced volume interconnect for three-dimensional chip stack

Method and structure of die stacking using pre-applied underfill

Ball grid array and land grid array assemblies fabricated using temporary resist

Assembly of a chip to a substrate

Underfill dispensing using funnels

Flip-chip bonder with induction coils and a heating element

Intraoral device control system

Remote based online product selection

Piezoelectric device powering smart contact lens with eyelid movement

Cognitive rotatable item storage with automated replenishment

Maintaining smart contact lens power levels

Active control of electronic package warpage

Flexible electronics for wearable healthcare sensors

Selective area heating for 3D chip stack

Flip chip assembly apparatus employing a warpage-suppressor assembly

Chip-to-wafer integration technology for three-dimensional chip stacking

Sintering a nanoparticle paste for semiconductor chip join

High density interconnection and wiring layers, package structures, and integration methods

Electronic package structure with offset stacked chips and top and bottom side cooling lid

Modular sensing unit

Asymmetric die bonding

Mitigating cooldown peeling stress during chip package assembly

Infrared debond damage mitigation by copper fill pattern

Quantifying grip strength and characterizing movement idioms

GLOBALFOUNDRIES INC

Structure for establishing interconnects in packages using thin interposers

Method for establishing interconnects in packages using thin interposers

Visualization of alignment marks on a chip covered by a pre-applied underfill

BROFMAN PETER J

Flip chip assembly apparatus employing a warpage-suppressor assembly

SAKUMA KATSUYUKI

Formation of through-silicon via (TSV) in silicon substrate