Inventor

LYNCH WILLIAM T

US34 patents

⚠️ This page may combine multiple inventors who share the name “LYNCH WILLIAM T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LYNCH WILLIAM T

AT & T BELL LAB

Method for fabricating semiconductor devices which include sources and drains having metal-containing material regions, and the resulting devices

Fabrication of schottky-barrier MOS FETs

Selective epitaxy of silicon in silicon dioxide apertures with suppression of unwanted formation of facets

Self aligned registration marks for integrated circuit fabrication

Laterally marching interconnecting lines in semiconductor intergrated circuits

Fabrication of FETs

Method for manufacturing an insulated gate field effect transistor device

Selective epitaxy of silicon in silicon dioxide apertures with suppression of unwanted formation of facets

Latchup-preventing CMOS device

Forming thick dielectric at the bottoms of trenches utilized in integrated-circuit devices

Formation of integrated circuit electrodes

Radiation-sensitive device

Fabrication of FETs

Devices having shallow junctions

Latchup-preventing CMOS device

AMERICAN TELEPHONE & TELEGRAPH

Test circuit for measuring specific contact resistivity of self-aligned contacts in integrated circuits

Methods for fabricating latchup-preventing CMOS device

Fabrication of FETs with source and drain contacts aligned with the gate electrode

Radiation hardened semiconductor devices

Process for manufacturing semiconductor BICMOS device

Method for fabricating CMOS devices

Method of making high-performance trench capacitors for DRAM cells

Method of making high-performance dram arrays including trench capacitors

Schottky-barrier MOS devices

COMPAQ COMPUTER CORP

Method and apparatus for entering and manipulating spreadsheet cell data

Method and apparatus for entering and manipulating spreadsheet cell data

UNIV CALIFORNIA

Method of fabricating quantum bridges by selective etching of superlattice structures

Quantum bridges fabricated by selective etching of superlattice structures

BELL TELEPHONE LABOR INC

Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features

UNIV LELAND STANFORD JUNIOR

Method of shallow junction formation in semiconductor devices using gas immersion laser doping

UNIV DUKE

Method of forming metal-disilicide layers and contacts

UNIV TEXAS

P-I-N MOSFET for ULSI applications

IBM

System and method remapping identifiers to secure files

AT & T CORP

Planar isolation technique for integrated circuits