Inventor
BARAJAS SAUL
US17 patents
Patents
17 patentsUS5553263ASep 3, 1996
Cache memory system with fault tolerance having concurrently operational cache controllers processing disjoint groups of memory
UNISYS CORP60 citations95
US5506967AApr 9, 1996
Storage queue with adjustable level thresholds for cache invalidation systems in cache oriented computer architectures
UNISYS CORP59 citations95
US5598551AJan 28, 1997
Cache invalidation sequence system utilizing odd and even invalidation queues with shorter invalidation cycles
UNISYS CORP72 citations94
US5459836AOct 17, 1995
Inter-processor communication net
UNISYS CORP25 citations92
US5146596ASep 8, 1992
Multiprocessor multifunction arbitration system with two levels of bus access including priority and normal requests
UNISYS CORP37 citations92
US5086427AFeb 4, 1992
Clocked logic circuitry preventing double driving on shared data bus
UNISYS CORP36 citations92
US5689680ANov 18, 1997
Cache memory system and method for accessing a coincident cache with a bit-sliced architecture
UNISYS CORP9 citations73
US5561773AOct 1, 1996
Programmable, multi-purpose virtual pin multiplier
UNISYS CORP14 citations73
US5553259ASep 3, 1996
Apparatus and method for synchronizing the simultaneous loading of cache program word addresses in dual slice registers
UNISYS CORP8 citations73
US5418935AMay 23, 1995
Apparatus for preventing double drive occurrences on a common bus by delaying enablement of one driver after indication of disablement to other driver is received
UNISYS CORP9 citations73
US5321814AJun 14, 1994
System for optional module detection and reconfiguration
UNISYS CORP16 citations73
US5117132AMay 26, 1992
Flexible utilization of general flip-flops in programmable array logic
UNISYS CORP7 citations73
US5087839AFeb 11, 1992
Method of providing flexibility and alterability in VLSI gate array chips
UNISYS CORP6 citations73
US5087953AFeb 11, 1992
Flexible gate array system for combinatorial logic
UNISYS CORP9 citations73
US6070166AMay 30, 2000
Apparatus and method for compressing a plurality of contiguous addresses to form a compressed block address using the first address of the contiguous addresses and a block identifier bit
UNISYS CORP12 citations70
US5642486AJun 24, 1997
Invalidation queue with "bit-sliceability"
UNISYS CORP1 citations51
US5991853ANov 23, 1999
Methods for accessing coincident cache with a bit-sliced architecture
UNISYS CORP0 citations48