Inventor
KALISH DAVID M
US7 patents
Patents
7 patentsUS5553263ASep 3, 1996
Cache memory system with fault tolerance having concurrently operational cache controllers processing disjoint groups of memory
UNISYS CORP60 citations95
US5506967AApr 9, 1996
Storage queue with adjustable level thresholds for cache invalidation systems in cache oriented computer architectures
UNISYS CORP59 citations95
US5598551AJan 28, 1997
Cache invalidation sequence system utilizing odd and even invalidation queues with shorter invalidation cycles
UNISYS CORP72 citations94
US5689680ANov 18, 1997
Cache memory system and method for accessing a coincident cache with a bit-sliced architecture
UNISYS CORP9 citations73
US5561773AOct 1, 1996
Programmable, multi-purpose virtual pin multiplier
UNISYS CORP14 citations73
US5553259ASep 3, 1996
Apparatus and method for synchronizing the simultaneous loading of cache program word addresses in dual slice registers
UNISYS CORP8 citations73
US5642486AJun 24, 1997
Invalidation queue with "bit-sliceability"
UNISYS CORP1 citations51