Inventor

WHITTAKER BRUCE E

US24 patents

⚠️ This page may combine multiple inventors who share the name “WHITTAKER BRUCE E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WHITTAKER BRUCE E

UNISYS CORP

Storage queue with adjustable level thresholds for cache invalidation systems in cache oriented computer architectures

System for halting synchronous digital modules

Cache invalidation sequence system utilizing odd and even invalidation queues with shorter invalidation cycles

Inter-processor communication net

Multiprocessor multifunction arbitration system with two levels of bus access including priority and normal requests

Clocked logic circuitry preventing double driving on shared data bus

Cache memory system and method for accessing a coincident cache with a bit-sliced architecture

Programmable, multi-purpose virtual pin multiplier

Apparatus for preventing double drive occurrences on a common bus by delaying enablement of one driver after indication of disablement to other driver is received

System for optional module detection and reconfiguration

System for memory data integrity

Flexible utilization of general flip-flops in programmable array logic

Width-expansible memory integrity structure

Method of providing flexibility and alterability in VLSI gate array chips

Flexible gate array system for combinatorial logic

Multiple memory bank parity checking system

Mini cache operational module for enhancement to general cache

Apparatus and method for compressing a plurality of contiguous addresses to form a compressed block address using the first address of the contiguous addresses and a block identifier bit

Invalidation queue with &#34;bit-sliceability&#34;

Methods for accessing coincident cache with a bit-sliced architecture

Half synchronizer circuit interface system

BURROUGHS CORP

Power control network for multiple digital modules

Power control network using reliable communications protocol

System control network for multiple processor modules

Invalidation queue with "bit-sliceability"