Inventor

MATHEWSON BRUCE JAMES

GB51 patents

⚠️ This page may combine multiple inventors who share the name “MATHEWSON BRUCE JAMES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MATHEWSON BRUCE JAMES

ADVANCED RISC MACH LTD

Method of arbitrating between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit of a data processing apparatus

Flexibility of use of a data processing apparatus

Interface circuitry for exchanging information with master, home, and slave nodes using different data transfer protocols

Flexibility of design of a bus interconnect block for a data processing apparatus

Data processing apparatus and method for managing snoop operations

Message handling communication between a source processor core and destination processor cores

Apparatus and method for handling cache maintenance operations

Access control

Read-with overridable-invalidate transaction

Data processing system and method for handling multiple transactions using a multi-transaction request

Bus transaction management within data processing systems

Memory interface having data signal path and tag signal path

Filtering coherency protocol transactions

Technique for handling protocol conversion

Cache for storing coherent and non-coherent data

Cache content management

Read transaction tracker lifetimes in a coherent interconnect system

Separating completion and data responses for higher read throughput and lower link utilization in a data processing network

Barrier transactions in interconnects

Control of master/slave communication within an integrated circuit

Handling of write transactions in a data processing apparatus

Performing arbitration in a data processing apparatus

Write transaction interleaving

Write response signalling within a communication bus

Data processing system for a home node to authorize a master to bypass the home node to directly send data to a slave

Apparatus and method to schedule time-sensitive tasks

Core-to-core cache stashing and target discovery

Writing zero data

Forwarding responses to snoop requests

Apparatus and method for performing cache maintenance over a virtual page

Transfer protocol in a data processing network

Responding to snoop requests

Cache bypass

Exclusivity in circuitry having a home node providing coherency control

Interconnect circuitry and a method of operating such interconnect circuitry

Apparatus and method for handling data in a cache

Data processing apparatus and method for address translation

Non-forwardable transfers

Runtime configuration of a data processing system

Data processing

Cache maintenance operations in a data processing system

Compare-and-swap transaction

Bit ordering for packetised serial data transmission on an integrated circuit

RIOCREUX PETER ANDREW

Synchronising activities of various components in a distributed system

Reduced latency barrier transaction requests in interconnects

Data store maintenance requests in interconnects

Barrier transactions in interconnects

HARRIS ANTONY JOHN

Interconnect logic for a data processing apparatus

MANNAVA PHANINDRA KUMAR

Dynamic resource allocation for transaction requests issued by initiator devices to recipient devices

BILES STUART DAVID

Store-exclusive instruction conflict resolution