Inventor
TRAGER BARRY M
US30 patents
⚠️ This page may combine multiple inventors who share the name “TRAGER BARRY M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
8 patentsUS10606692B2Mar 31, 2020
Error correction potency improvement via added burst beats in a dram access cycle
IBM8 citations84
US10303545B1May 28, 2019
High efficiency redundant array of independent memory
IBM11 citations84
US8352806B2Jan 8, 2013
System to improve memory failure management and associated methods
IBM12 citations84
US8010875B2Aug 30, 2011
Error correcting code with chip kill capability and power saving enhancement
IBM19 citations83
US10901839B2Jan 26, 2021
Common high and low random bit error correction logic
IBM1 citations62
US10824508B2Nov 3, 2020
High efficiency redundant array of independent memory
IBM1 citations62
US10824504B2Nov 3, 2020
Common high and low random bit error correction logic
IBM0 citations39
US10601448B2Mar 24, 2020
Reduced latency error correction decoding
IBM0 citations36
CHANDU KARTHEEK
6 patentsUS8773722B2Jul 8, 2014
Hybrid halftone generation mechanism using change in pixel error
CHANDU KARTHEEK2 citations62
US9614998B2Apr 4, 2017
Mechanism for generating a hybrid halftone using a DMSSA screen
CHANDU KARTHEEK0 citations52
US9363414B2Jun 7, 2016
Halftone mechanism
CHANDU KARTHEEK0 citations52
US8922834B2Dec 30, 2014
Hybrid halftone generation mechanism using change in pixel error
CHANDU KARTHEEK1 citations52
US8693054B2Apr 8, 2014
Mask generation mechanism
CHANDU KARTHEEK0 citations52
US9036212B2May 19, 2015
Halftone screen generation mechanism
CHANDU KARTHEEK0 citations41