Inventor
JALEEL AAMER
US25 patents
⚠️ This page may combine multiple inventors who share the name “JALEEL AAMER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
12 patentsUS7725657B2May 25, 2010
Dynamic quality of service (QoS) for a shared cache
INTEL CORP33 citations92
US10331583B2Jun 25, 2019
Executing distributed memory operations using processing elements connected by distributed channels
INTEL CORP26 citations90
US8347301B2Jan 1, 2013
Device, system, and method of scheduling tasks of a multithreaded application
INTEL CORP15 citations84
US10387319B2Aug 20, 2019
Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features
INTEL CORP9 citations82
US10284470B2May 7, 2019
Technologies for network device flow lookup management
INTEL CORP2 citations73
US9792212B2Oct 17, 2017
Virtual shared cache mechanism in a processing device
INTEL CORP2 citations73
US10102134B2Oct 16, 2018
Instruction and logic for run-time evaluation of multiple prefetchers
INTEL CORP5 citations71
US11513957B2Nov 29, 2022
Processor and method implementing a cacheline demote machine instruction
INTEL CORP0 citations62
US10853276B2Dec 1, 2020
Executing distributed memory operations using processing elements connected by distributed channels
INTEL CORP1 citations59
US10817425B2Oct 27, 2020
Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads
INTEL CORP0 citations52
US9286128B2Mar 15, 2016
Processor scheduling with thread performance estimation on cores of different types
INTEL CORP0 citations49
US9710380B2Jul 18, 2017
Managing shared cache by multi-core processor
INTEL CORP0 citations40
NVIDIA CORP
4 patentsUS12135781B2Nov 5, 2024
Implementing hardware-based memory safety for a graphic processing unit
NVIDIA CORP0 citations60
US12321230B2Jun 3, 2025
Alias-free tagged error correcting codes for machine memory operations
NVIDIA CORP0 citations58
US12596798B2Apr 7, 2026
Probabilistic tracker management for memory attack mitigation
NVIDIA CORP0 citations50
US11836361B2Dec 5, 2023
Implementing compiler-based memory safety for a graphic processing unit
NVIDIA CORP0 citations50