Inventor
DOU XINYUAN
US15 patents
⚠️ This page may combine multiple inventors who share the name “DOU XINYUAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
GLOBALFOUNDRIES INC
14 patentsUS10014296B1Jul 3, 2018
Fin-type field effect transistors with single-diffusion breaks and method
GLOBALFOUNDRIES INC19 citations85
US10090382B1Oct 2, 2018
Integrated circuit structure including single diffusion break and end isolation region, and methods of forming same
GLOBALFOUNDRIES INC14 citations84
US10074732B1Sep 11, 2018
Methods of forming short channel and long channel finFET devices so as to adjust threshold voltages
GLOBALFOUNDRIES INC11 citations83
US10083873B1Sep 25, 2018
Semiconductor structure with uniform gate heights
GLOBALFOUNDRIES INC5 citations73
US10043713B1Aug 7, 2018
Method to reduce FinFET short channel gate height
GLOBALFOUNDRIES INC4 citations73
US10580857B2Mar 3, 2020
Method to form high performance fin profile for 12LP and above
GLOBALFOUNDRIES INC3 citations72
US10522679B2Dec 31, 2019
Selective shallow trench isolation (STI) fill for stress engineering in semiconductor structures
GLOBALFOUNDRIES INC6 citations69
US9831098B2Nov 28, 2017
Methods for fabricating integrated circuits using flowable chemical vapor deposition techniques with low-temperature thermal annealing
GLOBALFOUNDRIES INC3 citations67
US10818557B2Oct 27, 2020
Integrated circuit structure to reduce soft-fail incidence and method of forming same
GLOBALFOUNDRIES INC1 citations60
US10643900B2May 5, 2020
Method to reduce FinFET short channel gate height
GLOBALFOUNDRIES INC0 citations52
US10910276B1Feb 2, 2021
STI structure with liner along lower portion of longitudinal sides of active region, and related FET and method
GLOBALFOUNDRIES INC0 citations51
US10714380B2Jul 14, 2020
Method of forming smooth sidewall structures using spacer materials
GLOBALFOUNDRIES INC0 citations51
US10347531B2Jul 9, 2019
Middle of the line (MOL) contact formation method and structure
GLOBALFOUNDRIES INC0 citations51
US10153211B1Dec 11, 2018
Methods, apparatus, and system for fabricating finFET devices with increased breakdown voltage
GLOBALFOUNDRIES INC0 citations40