Inventor
GROCHOWSKI EDWARD
US31 patents
⚠️ This page may combine multiple inventors who share the name “GROCHOWSKI EDWARD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
29 patentsUS7437581B2Oct 14, 2008
Method and apparatus for varying energy per instruction according to the amount of available parallelism
INTEL CORP138 citations97
US6035389AMar 7, 2000
Scheduling instructions with different latencies
INTEL CORP98 citations97
US5450605ASep 12, 1995
Boundary markers for indicating the boundary of a variable length instruction to facilitate parallel processing of sequential instructions
INTEL CORP60 citations95
US7480838B1Jan 20, 2009
Method, system and apparatus for detecting and recovering from timing errors
INTEL CORP29 citations92
US6754689B2Jun 22, 2004
Method and apparatus for performing subtraction in redundant form arithmetic
INTEL CORP29 citations92
US5586276ADec 17, 1996
End bit markers for indicating the end of a variable length instruction to facilitate parallel processing of sequential instructions
INTEL CORP29 citations92
US5581718ADec 3, 1996
Method and apparatus for selecting instructions for simultaneous execution
INTEL CORP41 citations92
US5535347AJul 9, 1996
Rotators in machine instruction length calculation
INTEL CORP36 citations87
US10585667B2Mar 10, 2020
Method and system to provide user-level multithreading
INTEL CORP7 citations83
US7622961B2Nov 24, 2009
Method and apparatus for late timing transition detection
INTEL CORP15 citations83
US9990206B2Jun 5, 2018
Mechanism for instruction set based thread execution of a plurality of instruction sequencers
INTEL CORP8 citations82
US6675266B2Jan 6, 2004
Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors
INTEL CORP11 citations81
US6813628B2Nov 2, 2004
Method and apparatus for performing equality comparison in redundant form arithmetic
INTEL CORP12 citations74
US4985640AJan 15, 1991
Apparatus for generating computer clock pulses
INTEL CORP14 citations74
US6938126B2Aug 30, 2005
Cache-line reuse-buffer
INTEL CORP7 citations73
US6904502B2Jun 7, 2005
Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors
INTEL CORP4 citations73
US6775746B2Aug 10, 2004
Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors
INTEL CORP4 citations73
US10445244B2Oct 15, 2019
Method, system, and apparatus for page sizing extension
INTEL CORP1 citations71
US6826588B2Nov 30, 2004
Method and apparatus for a fast comparison in redundant form arithmetic
INTEL CORP6 citations63
US6763368B2Jul 13, 2004
Method and apparatus for performing single-cycle addition or subtraction and comparison in redundant form arithmetic
INTEL CORP2 citations63
US7315920B2Jan 1, 2008
Circuit and method for protecting vector tags in high performance microprocessors
INTEL CORP2 citations62
US9934155B2Apr 3, 2018
Method, system, and apparatus for page sizing extension
INTEL CORP1 citations61
US6954848B2Oct 11, 2005
Marking in history table instructions slowable/delayable for subsequent executions when result is not used immediately
INTEL CORP3 citations60
US7395304B2Jul 1, 2008
Method and apparatus for performing single-cycle addition or subtraction and comparison in redundant form arithmetic
INTEL CORP0 citations52
US10635438B2Apr 28, 2020
Method and system to provide user-level multithreading
INTEL CORP0 citations51
US10628153B2Apr 21, 2020
Method and system to provide user-level multithreading
INTEL CORP0 citations51
US10613858B2Apr 7, 2020
Method and system to provide user-level multithreading
INTEL CORP0 citations51
US10445245B2Oct 15, 2019
Method, system, and apparatus for page sizing extension
INTEL CORP0 citations51
US6839814B2Jan 4, 2005
Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors
INTEL CORP0 citations51