Inventor
SHEN JOHN P
US39 patents
⚠️ This page may combine multiple inventors who share the name “SHEN JOHN P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
26 patentsUS8010969B2Aug 30, 2011
Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers
INTEL CORP16 citations92
US7814469B2Oct 12, 2010
Speculative multi-threading for instruction prefetch and/or trace pre-build
INTEL CORP13 citations92
US7404067B2Jul 22, 2008
Method and apparatus for efficient utilization for prescient instruction prefetch
INTEL CORP25 citations92
US7398521B2Jul 8, 2008
Methods and apparatuses for thread management of multi-threading
INTEL CORP26 citations92
US7363467B2Apr 22, 2008
Dependence-chain processing using trace descriptors having dependency descriptors
INTEL CORP40 citations92
US6928645B2Aug 9, 2005
Software-based speculative pre-computation and multithreading
INTEL CORP48 citations91
US7631307B2Dec 8, 2009
User-programmable low-overhead multithreading
INTEL CORP44 citations88
US10585667B2Mar 10, 2020
Method and system to provide user-level multithreading
INTEL CORP7 citations83
US7228528B2Jun 5, 2007
Building inter-block streams from a dynamic execution trace for a program
INTEL CORP13 citations83
US7818547B2Oct 19, 2010
Method and apparatus for efficient resource utilization for prescient instruction prefetch
INTEL CORP7 citations73
US10877910B2Dec 29, 2020
Programmable event driven yield mechanism which may activate other threads
INTEL CORP1 citations72
US10459858B2Oct 29, 2019
Programmable event driven yield mechanism which may activate other threads
INTEL CORP1 citations72
US9910796B2Mar 6, 2018
Programmable event driven yield mechanism which may activate other threads
INTEL CORP1 citations62
US7991965B2Aug 2, 2011
Technique for using memory attributes
INTEL CORP1 citations61
US7844801B2Nov 30, 2010
Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors
INTEL CORP2 citations61
US6668306B2Dec 23, 2003
Non-vital loads
INTEL CORP5 citations60
US9069605B2Jun 30, 2015
Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention
INTEL CORP1 citations52
US10635438B2Apr 28, 2020
Method and system to provide user-level multithreading
INTEL CORP0 citations51
US10628153B2Apr 21, 2020
Method and system to provide user-level multithreading
INTEL CORP0 citations51
US10613858B2Apr 7, 2020
Method and system to provide user-level multithreading
INTEL CORP0 citations51
US10452403B2Oct 22, 2019
Mechanism for instruction set based thread execution on a plurality of instruction sequencers
INTEL CORP0 citations51
US9952859B2Apr 24, 2018
Method and system to provide user-level multithreading
INTEL CORP0 citations51
US7424576B2Sep 9, 2008
Parallel cachelets
INTEL CORP0 citations50
US7216201B2May 8, 2007
Parallel cachelets
INTEL CORP0 citations50
US9442721B2Sep 13, 2016
Method and system to provide user-level multithreading
INTEL CORP0 citations49
US8812792B2Aug 19, 2014
Technique for using memory attributes
INTEL CORP0 citations48
HANKINS RICHARD A
3 patentsUS8887174B2Nov 11, 2014
Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers
HANKINS RICHARD A2 citations61
US8607235B2Dec 10, 2013
Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention
HANKINS RICHARD A3 citations61
US8079035B2Dec 13, 2011
Data structure and management techniques for local user-level thread data
HANKINS RICHARD A5 citations60