Inventor
BEARDSLEE JOHN MARK
US38 patents
⚠️ This page may combine multiple inventors who share the name “BEARDSLEE JOHN MARK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
COHERENT LOGIX INC
18 patentsUS9430369B2Aug 30, 2016
Memory-network processor with programmable optimizations
COHERENT LOGIX INC20 citations92
US9195575B2Nov 24, 2015
Dynamic reconfiguration of applications on a multi-processor embedded system
COHERENT LOGIX INC6 citations81
US11544072B2Jan 3, 2023
Memory-network processor with programmable optimizations
COHERENT LOGIX INC2 citations72
US11914989B2Feb 27, 2024
Multiprocessor programming toolkit for design reuse
COHERENT LOGIX INC1 citations70
US11720479B2Aug 8, 2023
Real time analysis and control for a multiprocessor system
COHERENT LOGIX INC1 citations69
US9250867B2Feb 2, 2016
Programming a multi-processor system
COHERENT LOGIX INC1 citations63
US11900124B2Feb 13, 2024
Memory-network processor with programmable optimizations
COHERENT LOGIX INC0 citations62
US11016779B2May 25, 2021
Memory-network processor with programmable optimizations
COHERENT LOGIX INC0 citations62
US11163558B2Nov 2, 2021
Multiprocessor programming toolkit for design reuse
COHERENT LOGIX INC0 citations60
US11726812B2Aug 15, 2023
Dynamic reconfiguration of applications on a multi-processor embedded system
COHERENT LOGIX INC0 citations59
US11023272B2Jun 1, 2021
Dynamic reconfiguration of applications on a multi-processor embedded system
COHERENT LOGIX INC0 citations59
US10776085B2Sep 15, 2020
Programming a multi-processor system
COHERENT LOGIX INC0 citations52
US9965258B2May 8, 2018
Programming a multi-processor system
COHERENT LOGIX INC0 citations52
US10592233B2Mar 17, 2020
Multiprocessor programming toolkit for design reuse
COHERENT LOGIX INC0 citations49
US9990227B2Jun 5, 2018
Dynamic reconfiguration of applications on a multi-processor embedded system
COHERENT LOGIX INC0 citations49
US9904542B2Feb 27, 2018
Multiprocessor programming toolkit for design reuse
COHERENT LOGIX INC0 citations49
US10114739B2Oct 30, 2018
Real time analysis and control for a multiprocessor system
COHERENT LOGIX INC0 citations48
US9477585B2Oct 25, 2016
Real time analysis and control for a multiprocessor system
COHERENT LOGIX INC1 citations48
SYNPLICITY INC
11 patentsUS6618839B1Sep 9, 2003
Method and system for providing an electronic system design with enhanced debugging capabilities
SYNPLICITY INC195 citations98
US6581191B1Jun 17, 2003
Hardware debugging in a hardware description language
SYNPLICITY INC227 citations98
US7240303B1Jul 3, 2007
Hardware/software co-debugging in a hardware description language
SYNPLICITY INC132 citations97
US7072818B1Jul 4, 2006
Method and system for debugging an electronic system
SYNPLICITY INC94 citations97
US6823497B2Nov 23, 2004
Method and user interface for debugging an electronic system
SYNPLICITY INC170 citations97
US7069526B2Jun 27, 2006
Hardware debugging in a hardware description language
SYNPLICITY INC46 citations96
US6904577B2Jun 7, 2005
Hardware debugging in a hardware description language
SYNPLICITY INC41 citations96
US7065481B2Jun 20, 2006
Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzer
SYNPLICITY INC59 citations94
US6931572B1Aug 16, 2005
Design instrumentation circuitry
SYNPLICITY INC35 citations92
US7356786B2Apr 8, 2008
Method and user interface for debugging an electronic system
SYNPLICITY INC30 citations91
US7222315B2May 22, 2007
Hardware-based HDL code coverage and design analysis
SYNPLICITY INC31 citations90
SYNOPSYS INC
3 patentsUS7827510B1Nov 2, 2010
Enhanced hardware debugging with embedded FPGAS in a hardware description language
SYNOPSYS INC88 citations97
US7506286B2Mar 17, 2009
Method and system for debugging an electronic system
SYNOPSYS INC36 citations92
US7836416B2Nov 16, 2010
Hardware-based HDL code coverage and design analysis
SYNOPSYS INC23 citations90
MYTHIC INC
2 patentsUS12205016B2Jan 21, 2025
Systems and methods for enhancing inferential accuracy of an artificial neural network during training on a mixed-signal integrated circuit
MYTHIC INC0 citations56
US11720784B2Aug 8, 2023
Systems and methods for enhancing inferential accuracy of an artificial neural network during training on a mixed-signal integrated circuit
MYTHIC INC0 citations56