Inventor

SCHUSTER STANLEY E

US40 patents

Patents

40 patents

US4845677AJul 4, 1989

Processor with low overhead predictive supply voltage gating for leakage power reduction

IBM28 citations92

US5542067AJul 30, 1996

Virtual multi-port RAM employing multiple accesses during single machine cycle

IBM36 citations92

US5506457AApr 9, 1996

Electronic switch for decoupling capacitor

IBM27 citations92

US5388072AFeb 7, 1995

Bit line switch array for electronic computer memory

IBM32 citations92

US4843261AJun 27, 1989

Complementary output, high-density CMOS decoder/driver circuit for semiconductor memories

IBM29 citations92

US4763180AAug 9, 1988

Method and structure for a high density VMOS dynamic ram array

IBM27 citations92

US4645954AFeb 24, 1987

ECL to FET interface circuit for field effect transistor arrays

IBM28 citations92

US4599708AJul 8, 1986

Method and structure for machine data storage with simultaneous write and read

IBM28 citations92

US7076681B2Jul 11, 2006

Processor with demand-driven clock throttling power reduction

IBM31 citations91

US7865747B2Jan 4, 2011

Adaptive issue queue for reduced power at high performance

IBM11 citations84

US7308593B2Dec 11, 2007

Interlocked synchronous pipeline clock gating

IBM10 citations84

US7289369B2Oct 30, 2007

DRAM hierarchical data path

IBM12 citations84

US4618784AOct 21, 1986

High-performance, high-density CMOS decoder/driver circuit

IBM21 citations82

US7821858B2Oct 26, 2010

eDRAM hierarchical differential sense AMP

IBM7 citations74

US7475227B2Jan 6, 2009

Method of stalling one or more stages in an interlocked synchronous pipeline

IBM5 citations74

US7471546B2Dec 30, 2008

Hierarchical six-transistor SRAM

IBM7 citations74

US7460387B2Dec 2, 2008

eDRAM hierarchical differential sense amp

IBM8 citations74

US5471188ANov 28, 1995

Fast comparator circuit

IBM7 citations74

US5089726AFeb 18, 1992

Fast cycle time clocked amplifier

IBM7 citations74

US5015881AMay 14, 1991

High speed decoding circuit with improved AND gate

IBM19 citations74

US4998028AMar 5, 1991

High speed CMOS logic device for providing ECL compatible logic levels

IBM9 citations74

US4835419AMay 30, 1989

Source-follower emitter-coupled-logic receiver circuit

IBM9 citations74

US4719372AJan 12, 1988

Multiplying interface circuit for level shifting between FET and TTL levels

IBM9 citations74

US4491748AJan 1, 1985

High performance FET driver circuit

IBM13 citations74

US4441039AApr 3, 1984

Input buffer circuit for semiconductor memory

IBM12 citations74

US4199695AApr 22, 1980

Avoidance of hot electron operation of voltage stressed bootstrap drivers

IBM15 citations74

US5434519AJul 18, 1995

Self-resetting CMOS off-chip driver

IBM17 citations73

US4028694AJun 7, 1977

A/D and D/A converter using C-2C ladder network

IBM20 citations73

US4833670AMay 23, 1989

Cross-point bit-switch for communication

IBM12 citations70

US7460423B2Dec 2, 2008

Hierarchical 2T-DRAM with self-timed sensing

IBM2 citations63

US6829716B2Dec 7, 2004

Latch structure for interlocked pipelined CMOS (IPCMOS) circuits

IBM4 citations63

US4697108ASep 29, 1987

Complementary input circuit with nonlinear front end and partially coupled latch

IBM6 citations63

US4295064AOct 13, 1981

Logic and array logic driving circuits

IBM3 citations63

US7709299B2May 4, 2010

Hierarchical 2T-DRAM with self-timed sensing

IBM1 citations52

SCHUSTER STANLEY E

Patents

Pipelined memory chip structure having improved cycle time

Interlocked synchronous pipeline clock gating

Synchronous to asynchronous to synchronous interface

Virtual multi-port RAM

Interlocked synchronous pipeline clock gating

Fast, stable, SRAM cell using seven devices and hierarchical bit/sense line

Processor with low overhead predictive supply voltage gating for leakage power reduction

Virtual multi-port RAM employing multiple accesses during single machine cycle

Electronic switch for decoupling capacitor

Bit line switch array for electronic computer memory

Complementary output, high-density CMOS decoder/driver circuit for semiconductor memories

Method and structure for a high density VMOS dynamic ram array

ECL to FET interface circuit for field effect transistor arrays

Method and structure for machine data storage with simultaneous write and read

Processor with demand-driven clock throttling power reduction

Adaptive issue queue for reduced power at high performance

Interlocked synchronous pipeline clock gating

DRAM hierarchical data path

High-performance, high-density CMOS decoder/driver circuit

eDRAM hierarchical differential sense AMP

Method of stalling one or more stages in an interlocked synchronous pipeline

Hierarchical six-transistor SRAM

eDRAM hierarchical differential sense amp

Fast comparator circuit

Fast cycle time clocked amplifier

High speed decoding circuit with improved AND gate

High speed CMOS logic device for providing ECL compatible logic levels

Source-follower emitter-coupled-logic receiver circuit

Multiplying interface circuit for level shifting between FET and TTL levels

High performance FET driver circuit

Input buffer circuit for semiconductor memory

Avoidance of hot electron operation of voltage stressed bootstrap drivers

Self-resetting CMOS off-chip driver

A/D and D/A converter using C-2C ladder network

Cross-point bit-switch for communication

Hierarchical 2T-DRAM with self-timed sensing

Latch structure for interlocked pipelined CMOS (IPCMOS) circuits

Complementary input circuit with nonlinear front end and partially coupled latch

Logic and array logic driving circuits

Hierarchical 2T-DRAM with self-timed sensing