Inventor · disambiguated record
Rajeev Joshi
Also filed as: JOSHI RAJEEV · JOSHI RAJEEV D · JOSHI RAJEEV DINKAR
81 granted patents·11 pending applications·4,259 citations·filing 1995–2025
99Inventor score
Files withFAIRCHILD SEMICONDUCTOR53TEXAS INSTRUMENTS INC14JOSHI RAJEEV8NAT SEMICONDUCTOR CORP4FAIRCHILD KR SEMICONDUCTOR LTD2
Top patents by PatentIndex Score
92 records- 0199US6992384B2High performance multi-chip flip chip packageFAIRCHILD SEMICONDUCTOR·Filed 2003·Granted Jan 31, 2006·111 cites·14 claims
- 0299US6696321B2High performance multi-chip flip chip packageFAIRCHILD SEMICONDUCTOR·Filed 2002·Granted Feb 24, 2004·142 cites·2 claims
- 0399US6627991B1High performance multi-chip flip packageFAIRCHILD SEMICONDUCTOR·Filed 2000·Granted Sep 30, 2003·170 cites·12 claims
- 0499US6489678B1High performance multi-chip flip chip packageFAIRCHILD SEMICONDUCTOR·Filed 1999·Granted Dec 3, 2002·213 cites·12 claims
- 0599US6133634AHigh performance flip chip packageFAIRCHILD SEMICONDUCTOR·Filed 1998·Granted Oct 17, 2000·336 cites·8 claims
- 0698US7215011B2Flip chip in leaded molded package and method of manufacture thereofFAIRCHILD SEMICONDUCTOR·Filed 2005·Granted May 8, 2007·65 cites·20 claims
- 0798US7081666B2Lead frame structure with aperture or groove for flip chip in a leaded molded packageFAIRCHILD SEMICONDUCTOR·Filed 2005·Granted Jul 25, 2006·92 cites·17 claims
- 0898US6891256B2Thin, thermally enhanced flip chip in a leaded molded packageFAIRCHILD SEMICONDUCTOR·Filed 2002·Granted May 10, 2005·167 cites·20 claims
- 0998US6731003B2Wafer-level coated copper stud bumpsFAIRCHILD SEMICONDUCTOR·Filed 2003·Granted May 4, 2004·279 cites·17 claims
- 1098US6683375B2Semiconductor die including conductive columnsFAIRCHILD SEMICONDUCTOR·Filed 2001·Granted Jan 27, 2004·149 cites·9 claims
- 1198US6469384B2Unmolded package for a semiconductor deviceFAIRCHILD SEMICONDUCTOR·Filed 2001·Granted Oct 22, 2002·103 cites·6 claims
- 1298US6294403B1High performance flip chip packageFiled 2000·Granted Sep 25, 2001·82 cites·4 claims
- 1397US9468087B1Power module with improved cooling and method for makingTEXAS INSTRUMENTS INC·Filed 2015·Granted Oct 11, 2016·22 cites·20 claims
- 1497US7332806B2Thin, thermally enhanced molded package with leadframe having protruding regionFAIRCHILD SEMICONDUCTOR·Filed 2005·Granted Feb 19, 2008·48 cites·13 claims
- 1597US7061077B2Substrate based unmolded package including lead frame structure and semiconductor dieFAIRCHILD SEMICONDUCTOR·Filed 2002·Granted Jun 13, 2006·93 cites·11 claims
- 1697US6566749B1Semiconductor die package with improved thermal and electrical performanceFAIRCHILD SEMICONDUCTOR·Filed 2002·Granted May 20, 2003·170 cites·22 claims
- 1796US8679896B2DC/DC converter power module package incorporating a stacked controller and construction methodologyNAT SEMICONDUCTOR CORP·Filed 2013·Granted Mar 25, 2014·23 cites·7 claims
- 1896US7618896B2Semiconductor die package including multiple dies and a common node structureFAIRCHILD SEMICONDUCTOR·Filed 2006·Granted Nov 17, 2009·36 cites·12 claims
- 1996US7271497B2Dual metal stud bumping for flip chip applicationsFAIRCHILD SEMICONDUCTOR·Filed 2003·Granted Sep 18, 2007·110 cites·13 claims
- 2096US7256479B2Method to manufacture a universal footprint for a package with exposed chipFAIRCHILD SEMICONDUCTOR·Filed 2005·Granted Aug 14, 2007·62 cites·17 claims
- 2196US7022548B2Method for making a semiconductor die packageFAIRCHILD SEMICONDUCTOR·Filed 2003·Granted Apr 4, 2006·92 cites·13 claims
- 2296US6867481B2Lead frame structure with aperture or groove for flip chip in a leaded molded packageFAIRCHILD SEMICONDUCTOR·Filed 2003·Granted Mar 15, 2005·105 cites·7 claims
- 2396US6806580B2Multichip module including substrate with an array of interconnect structuresFAIRCHILD SEMICONDUCTOR·Filed 2002·Granted Oct 19, 2004·102 cites·18 claims
- 2495US7315077B2Molded leadless package having a partially exposed lead frame padFAIRCHILD KR SEMICONDUCTOR LTD·Filed 2004·Granted Jan 1, 2008·107 cites·27 claims
- 2595US7196313B2Surface mount multi-channel optocouplerFAIRCHILD SEMICONDUCTOR·Filed 2004·Granted Mar 27, 2007·108 cites·27 claims
- 2695US6836023B2Structure of integrated trace of chip packageFAIRCHILD SEMICONDUCTOR·Filed 2003·Granted Dec 28, 2004·110 cites·20 claims
- 2795US6720642B1Flip chip in leaded molded package and method of manufacture thereofFAIRCHILD SEMICONDUCTOR·Filed 1999·Granted Apr 13, 2004·137 cites·7 claims
- 2894US8524532B1Integrated circuit package including an embedded power stage wherein a first field effect transistor (FET) and a second FET are electrically coupled thereinJOSHI RAJEEV·Filed 2012·Granted Sep 3, 2013·21 cites·16 claims
- 2994US8183088B2Semiconductor die package and method for making the sameJEON OSEOB·Filed 2010·Granted May 22, 2012·22 cites·14 claims
- 3094US7772681B2Semiconductor die package and method for making the sameFAIRCHILD SEMICONDUCTOR·Filed 2006·Granted Aug 10, 2010·25 cites·10 claims
- 3194US7504281B2Substrate based unmolded packageFAIRCHILD SEMICONDUCTOR·Filed 2005·Granted Mar 17, 2009·22 cites·14 claims
- 3294US7154168B2Flip chip in leaded molded package and method of manufacture thereofFAIRCHILD SEMICONDUCTOR·Filed 2003·Granted Dec 26, 2006·64 cites·12 claims
- 3393US6798044B2Flip chip in leaded molded package with two diesFAIRCHILD SEMICONDUCTOR·Filed 2000·Granted Sep 28, 2004·66 cites·8 claims
- 3492US7537958B1High performance multi-chip flip chip packageFAIRCHILD SEMICONDUCTOR·Filed 2005·Granted May 26, 2009·9 cites·15 claims
- 3592US5637916ACarrier based IC packaging arrangementNAT SEMICONDUCTOR CORP·Filed 1996·Granted Jun 10, 1997·114 cites·13 claims
- 3691US7468548B2Thermal enhanced upper and dual heat sink exposed molded leadless packageFAIRCHILD SEMICONDUCTOR·Filed 2005·Granted Dec 23, 2008·16 cites·15 claims
- 3790US7632719B2Wafer-level chip scale package and method for fabricating and using the sameFAIRCHILD KR SEMICONDUCTOR LTD·Filed 2009·Granted Dec 15, 2009·21 cites·15 claims
- 3890US6661082B1Flip chip substrate designFAIRCHILD SEMICONDUCTOR·Filed 2000·Granted Dec 9, 2003·71 cites·8 claims
- 3990US6633030B2Surface mountable optocoupler packageFAIRCHILD SEMICONDUCTOR·Filed 2001·Granted Oct 14, 2003·59 cites·19 claims
- 4089US6753605B2Passivation scheme for bumped wafersFAIRCHILD SEMICONDUCTOR·Filed 2000·Granted Jun 22, 2004·44 cites·3 claims
- 4189US5789809AThermally enhanced micro-ball grid array packageNAT SEMICONDUCTOR CORP·Filed 1995·Granted Aug 4, 1998·105 cites·13 claims
- 4288US7154186B2Multi-flip chip on lead frame on over molded IC package and method of assemblyFAIRCHILD SEMICONDUCTOR·Filed 2004·Granted Dec 26, 2006·42 cites·13 claims
- 4388US5765280AMethod for making a carrier based IC packaging arrangementNAT SEMICONDUCTOR CORP·Filed 1997·Granted Jun 16, 1998·86 cites·14 claims
- 4487US8664752B2Semiconductor die package and method for making the sameJEON OSEOB·Filed 2012·Granted Mar 4, 2014·9 cites·10 claims
- 4587US7439613B2Substrate based unmolded packageFAIRCHILD SEMICONDCUTOR CORP·Filed 2004·Granted Oct 21, 2008·36 cites·15 claims
- 4684US7968982B2Thermal enhanced upper and dual heat sink exposed molded leadless packageFAIRCHILD SEMICONDUCTOR·Filed 2008·Granted Jun 28, 2011·9 cites·16 claims
- 4784US6949410B2Flip chip in leaded molded package and method of manufacture thereofFAIRCHILD SEMICONDUCTOR·Filed 2003·Granted Sep 27, 2005·24 cites·20 claims
- 4883US8339231B1Leadframe based magnetics packageJOSHI RAJEEV·Filed 2010·Granted Dec 25, 2012·6 cites·21 claims
- 4983US7029947B2Flip chip in leaded molded package with two diesFAIRCHILD SEMICONDUCTOR·Filed 2004·Granted Apr 18, 2006·27 cites·7 claims
- 5082US7335532B2Method of assembly for multi-flip chip on lead frame on overmolded IC packageFAIRCHILD SEMICONDUCTOR·Filed 2006·Granted Feb 26, 2008·9 cites·2 claims
Showing the top 50 of 92 patent records by PatentIndex Score.
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