Inventor
AGARWAL VIKASH
US15 patents
⚠️ This page may combine multiple inventors who share the name “AGARWAL VIKASH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
BANK OF AMERICA
7 patentsUS11663399B1May 30, 2023
Platform for generating published reports with position mapping identification and template carryover reporting
BANK OF AMERICA3 citations68
US11983491B2May 14, 2024
Platform for generating published reports using report and worksheet building with position mapping identification
BANK OF AMERICA0 citations58
US11900054B1Feb 13, 2024
Platform for generating published reports using report and worksheet building with position mapping identification
BANK OF AMERICA1 citations58
US11983391B2May 14, 2024
System and method for data analysis and processing using identification tagging of information on a graphical user interface
BANK OF AMERICA0 citations47
US12566589B2Mar 3, 2026
System and method for determining data feed sources for interactive automated code generation and modification
BANK OF AMERICA0 citations46
US12411822B2Sep 9, 2025
System and method for determining and maintaining data quality in data processing
BANK OF AMERICA0 citations43
US12578933B2Mar 17, 2026
System and method for interactive automated code generation and modification for data processing
BANK OF AMERICA0 citations40
INTEL CORP
5 patentsUS10067762B2Sep 4, 2018
Apparatuses, methods, and systems for memory disambiguation
INTEL CORP4 citations71
US12190157B2Jan 7, 2025
Methods, systems, and apparatuses for scalable port-binding for asymmetric execution ports and allocation widths of a processor
INTEL CORP2 citations63
US11907712B2Feb 20, 2024
Methods, systems, and apparatuses for out-of-order access to a shared microcode sequencer by a clustered decode pipeline
INTEL CORP1 citations56
US12039329B2Jul 16, 2024
Methods, systems, and apparatuses to optimize partial flag updating instructions via dynamic two-pass execution in a processor
INTEL CORP0 citations46
US12353881B2Jul 8, 2025
Circuitry and methods for power efficient generation of length markers for a variable length instruction set
INTEL CORP0 citations45
CISCO TECH INC
2 patentsUS11824753B2Nov 21, 2023
Network node-to-node connectivity verification including data path processing of packets within a packet switching device
CISCO TECH INC2 citations70
US12273254B2Apr 8, 2025
Network node-to-node connectivity verification including data path processing of packets within a packet switching device
CISCO TECH INC1 citations61