Inventor

HUTTER LOUIS N

US40 patents

⚠️ This page may combine multiple inventors who share the name “HUTTER LOUIS N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUTTER LOUIS N

TEXAS INSTRUMENTS INC

Merged bipolar/CMOS technology using electrically active trench

Integrated circuit with bonding layer over active circuitry

Method of fabricating semiconductor device having polysilicon resistor with low temperature coefficient

LDMOS power device with oversized dwell

Semiconductor device having polysilicon resistor with low temperature coefficient

Method of fabricating semiconductor device having high-and low-voltage MOS transistors

Vertical DMOS transistor built in an n-well MOS-based BiCMOS process

Vertical DMOS transistor structure built in an N-well CMOS-based BiCMOS process and method of fabrication

Method of making vertical PNP transistor in merged bipolar/CMOS technology

Method for fabricating an isolated NMOS transistor on a digital BiCMOS process

High voltage Shottky diode

Method for fabricating a trench bipolar transistor

Merged trench bipolar-CMOS transistor fabrication process

Merged bipolar and CMOS circuit and method

Low voltage DMOS transistor

DMOS transistor with low on-resistance and method of fabrication

Vertical PNP transistor in merged bipolar/CMOS technology

Semiconductor process for manufacturing semiconductor devices with increased operating voltages

Deep trench isolation with surface contact to substrate

High voltage capacitor for integrated circuits

Integrated circuit capacitor and method

High voltage merged bipolar/CMOS technology

Tunnel diode layout for an EEPROM cell for protecting the tunnel diode region

Transistor with increased operating voltage and method of fabrication

Method for making an isolated vertical transistor

Power transistor with silicided gate and contacts

Semiconductor process for manufacturing semiconductor device with increased operating voltages

Trench bipolar transistor

Isolated NMOS transistor fabricated in a digital BiCMOS process

Self aligned DMOS transistor and method of fabrication

Isolated vertical PNP transistor and methods for making same in a digital BiCMOS process

Method for making an EEPROM with thermal oxide isolated floating gate

Semiconductor process for manufacturing semiconductor devices with increased operating voltages

Method of integrating a thin film resistor in a multi-level metal tungsten-plug interconnect

Semiconductor device with an analog capacitor

Method for making isolated vertical PNP transistor in a digital BiCMOS process

System and method for forming a semiconductor with an analog capacitor using fewer structure steps

Innovative method to build a high precision analog capacitor with low voltage coefficient and hysteresis

Substrate contact for gate array base cell and method of forming same

TEXAS INSTR INCOPORATED

Method of fabrication of a semiconductor device having high-and low-voltage MOS transistors