Inventor

VAN DYKE KORBIN S

US57 patents

⚠️ This page may combine multiple inventors who share the name “VAN DYKE KORBIN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VAN DYKE KORBIN S

ATI INT SRL

Recording classification of instructions executed by a computer

Modifying program execution based on profiling

Detecting modification to computer memory by a DMA device

Recording in a program execution profile references to a memory-mapped active device

Method and apparatus for restricting memory access

Detecting reordered side-effects

System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU

Profiling execution of computer programs

Profiling of computer programs executing in virtual memory systems

Method and apparatus for busing data elements

Computer for execution of RISC and CISC instruction sets

Exception mechanism for a computer

Profiling program execution into registers of a computer

Managing instruction side-effects

Safety net paradigm for managing two computer execution modes

Switching between a plurality of branch prediction processes based on which instruction set is operational wherein branch history data structures are the same for the plurality of instruction sets

ADVANCED MICRO DEVICES INC

Method and apparatus for debugging an integrated circuit

Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions

Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions

Method and apparatus for executing string instructions

Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts

Pipeline throughput via parallel out-of-order execution of adds and moves in a supplemental integer execution unit

Branch prediction cache with multiple entries for returns having multiple callers

Configurable branch prediction for a processor performing speculative execution

Branch prediction device with two levels of branch prediction cache

Branch prediction device with two levels of branch prediction cache

Configurable branch prediction for a processor performing speculative execution

Configurable branch prediction for a processor performing speculative execution

Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts

Superscalar execution unit for sequential instruction pointer updates and segment limit checks

Configurable branch prediction for a processor performing speculative execution

Cache memory system for dynamically altering single cache memory line as either branch target entry or prefetch instruction queue based upon instruction sequence

YATES JR JOHN S

Detecting conditions for transfer of execution from one computer instruction stream to another and executing transfer on satisfaction of the conditions

Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code

Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor

Apparatus for executing programs for a first computer architecture on a computer of a second architecture

Apparatus for executing programs for a first computer architechture on a computer of a second architechture

NEXGEN MICROSYSTEMS

Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence

Two-level branch prediction cache

Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags

Two-level branch prediction cache

NEXGEN INC

Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts

Configurable branch prediction for a processor performing speculative execution

Two-level branch prediction cache

VLSI TECHNOLOGY INC

Logarithmic conversion apparatus

Digital processor with a four part data register for storing data before and after data conversion and data calculations

ATI TECHNOLOGIES SRL

Side tables annotating an instruction stream

HESSEL RICHARD

Vector processor system

ATI TECHNOLOGIES ULC

Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination

HESSEL RICHARD EDWARD

Vector processor