Inventor
SPAETH MARK C
US3 patents
Patents
3 patentsUS6518800B2Feb 11, 2003
System and method for reducing timing mismatch in sample and hold circuits using the clock
TEXAS INSTRUMENTS INC21 citations90
US6407687B2Jun 18, 2002
System and method for reducing timing mismatch in sample and hold circuits using an FFT and subcircuit reassignment
TEXAS INSTRUMENTS INC25 citations90
US6483448B2Nov 19, 2002
System and method for reducing timing mismatch in sample and hold circuits using an FFT and decimation
TEXAS INSTRUMENTS INC19 citations82