Inventor
WALKER ROBERT F
US21 patents
⚠️ This page may combine multiple inventors who share the name “WALKER ROBERT F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
20 patentsUS7484197B2Jan 27, 2009
Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs
IBM297 citations98
US7302651B2Nov 27, 2007
Technology migration for integrated circuits with radical design restrictions
IBM209 citations98
US7503020B2Mar 10, 2009
IC layout optimization to improve yield
IBM110 citations97
US7363601B2Apr 22, 2008
Integrated circuit selective scaling
IBM19 citations92
US7257783B2Aug 14, 2007
Technology migration for integrated circuits with radical design restrictions
IBM12 citations92
US7062729B2Jun 13, 2006
Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization
IBM16 citations84
US7882463B2Feb 1, 2011
Integrated circuit selective scaling
IBM8 citations83
US7761821B2Jul 20, 2010
Technology migration for integrated circuits with radical design restrictions
IBM9 citations83
US7454721B2Nov 18, 2008
Method, apparatus and computer program product for optimizing an integrated circuit layout
IBM11 citations83
US7260790B2Aug 21, 2007
Integrated circuit yield enhancement using Voronoi diagrams
IBM15 citations83
US7610565B2Oct 27, 2009
Technology migration for integrated circuits with radical design restrictions
IBM6 citations73
US7117456B2Oct 3, 2006
Circuit area minimization using scaling
IBM7 citations73
US4516266AMay 7, 1985
Entity control for raster displays
IBM11 citations72
US7895562B2Feb 22, 2011
Adaptive weighting method for layout optimization with multiple priorities
IBM5 citations62
US7818694B2Oct 19, 2010
IC layout optimization to improve yield
IBM2 citations62
US7735042B2Jun 8, 2010
Context aware sub-circuit layout modification
IBM4 citations62
US7120887B2Oct 10, 2006
Cloned and original circuit shape merging
IBM5 citations62
US7865848B2Jan 4, 2011
Layout optimization using parameterized cells
IBM3 citations61
US7568173B2Jul 28, 2009
Independent migration of hierarchical designs with methods of finding and fixing opens during migration
IBM3 citations60
US7752589B2Jul 6, 2010
Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design
IBM0 citations51