Inventor
GUY BUFORD M
US11 patents
Patents
11 patentsUS10430193B2Oct 1, 2019
Packed data element predication processors, methods, systems, and instructions
INTEL CORP4 citations83
US10282296B2May 7, 2019
Zeroing a cache line
INTEL CORP7 citations83
US9990202B2Jun 5, 2018
Packed data element predication processors, methods, systems, and instructions
INTEL CORP6 citations83
US11442734B2Sep 13, 2022
Packed data element predication processors, methods, systems, and instructions
INTEL CORP2 citations72
US11294809B2Apr 5, 2022
Apparatuses and methods for a processor architecture
INTEL CORP2 citations72
US10963257B2Mar 30, 2021
Packed data element predication processors, methods, systems, and instructions
INTEL CORP2 citations72
US12130740B2Oct 29, 2024
Apparatuses and methods for a processor architecture
INTEL CORP0 citations62
US12039336B2Jul 16, 2024
Packed data element predication processors, methods, systems, and instructions
INTEL CORP0 citations62
US10228941B2Mar 12, 2019
Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger register
INTEL CORP0 citations51
US9934032B2Apr 3, 2018
Processors, methods, and systems to implement partial register accesses with masked full register accesses
INTEL CORP0 citations50
US9477467B2Oct 25, 2016
Processors, methods, and systems to implement partial register accesses with masked full register accesses
INTEL CORP0 citations50