Inventor
COLWELL MICHAEL J
US9 patents
⚠️ This page may combine multiple inventors who share the name “COLWELL MICHAEL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
6 patentsUS5698873ADec 16, 1997
High density gate array base cell architecture
LSI LOGIC CORP129 citations96
US5917207AJun 29, 1999
Programmable polysilicon gate array base cell architecture
LSI LOGIC CORP135 citations95
US5777354AJul 7, 1998
Low profile variable width input/output cells
LSI LOGIC CORP19 citations91
US5552333ASep 3, 1996
Method for designing low profile variable width input/output cells
LSI LOGIC CORP36 citations91
US5760428AJun 2, 1998
Variable width low profile gate array input/output architecture
LSI LOGIC CORP43 citations89
US5691218ANov 25, 1997
Method of fabricating a programmable polysilicon gate array base cell structure
LSI LOGIC CORP11 citations72
VIRAGE LOGIC CORP
3 patentsUS6617621B1Sep 9, 2003
Gate array architecture using elevated metal levels for customization
VIRAGE LOGIC CORP229 citations98
US6838713B1Jan 4, 2005
Dual-height cell with variable width power rail architecture
VIRAGE LOGIC CORP68 citations97
US7129562B1Oct 31, 2006
Dual-height cell with variable width power rail architecture
VIRAGE LOGIC CORP43 citations92