Inventor
STASIAK DANIEL LAWRENCE
US24 patents
⚠️ This page may combine multiple inventors who share the name “STASIAK DANIEL LAWRENCE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
22 patentsUS6504212B1Jan 7, 2003
Method and apparatus for enhanced SOI passgate operations
IBM85 citations97
US6002292ADec 14, 1999
Method and apparatus to control noise in a dynamic circuit
IBM77 citations96
US6934658B2Aug 23, 2005
Computer chip heat responsive method and apparatus
IBM20 citations92
US6429689B1Aug 6, 2002
Method and apparatus for controlling both active and standby power in domino circuits
IBM46 citations92
US6232799B1May 15, 2001
Method and apparatus for selectively controlling weak feedback in regenerative pass gate logic circuits
IBM18 citations92
US6201431B1Mar 13, 2001
Method and apparatus for automatically adjusting noise immunity of an integrated circuit
IBM30 citations92
US6925549B2Aug 2, 2005
Asynchronous pipeline control interface using tag values to control passing data through successive pipeline stages
IBM27 citations91
US6668358B2Dec 23, 2003
Dual threshold gate array or standard cell power saving library circuits
IBM41 citations88
US6635518B2Oct 21, 2003
SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologies
IBM15 citations84
US7044633B2May 16, 2006
Method to calibrate a chip with multiple temperature sensitive ring oscillators by calibrating only TSRO
IBM12 citations83
US6326814B1Dec 4, 2001
Method and apparatus for enhancing noise tolerance in dynamic silicon-on-insulator logic gates
IBM16 citations83
US7484187B2Jan 27, 2009
Clock-gating through data independent logic
IBM8 citations81
US6879928B2Apr 12, 2005
Method and apparatus to dynamically recalibrate VLSI chip thermal sensors through software control
IBM8 citations73
US6329846B1Dec 11, 2001
Cross-coupled dual rail dynamic logic circuit
IBM14 citations73
US7343499B2Mar 11, 2008
Method and apparatus to generate circuit energy models with multiple clock gating inputs
IBM6 citations71
US7656237B2Feb 2, 2010
Method to gate off PLLS in a deep power saving state without separate clock distribution for power management logic
IBM4 citations62
US6337584B1Jan 8, 2002
Method and apparatus for reducing bipolar current effects in silicon-on-insulator (SOI) dynamic logic circuits
IBM2 citations61
US7503025B2Mar 10, 2009
Method to generate circuit energy models for macros containing internal clock gating
IBM2 citations60
US7346866B2Mar 18, 2008
Method and apparatus to generate circuit energy models with clock gating
IBM5 citations60
US7284138B2Oct 16, 2007
Deep power saving by disabling clock distribution without separate clock distribution for power management logic
IBM1 citations51
US6407584B1Jun 18, 2002
Charge booster for CMOS dynamic circuits
IBM0 citations51
US7725744B2May 25, 2010
Method and apparatus to generate circuit energy models with multiple clock gating inputs
IBM1 citations50