Inventor

HOVIS WILLIAM P

US37 patents

⚠️ This page may combine multiple inventors who share the name “HOVIS WILLIAM P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOVIS WILLIAM P

IBM

Dynamic ram with on-chip ecc and optimized bit and word redundancy

System and method for memory self-timed refresh for reduced power consumption

Multi-level memory architecture with data prioritization

Multiple mode-set for IC chip

Setting memory device VREF in a memory controller and memory device interface in a communication bus

Calibration of memory driver with offset in a memory controller and memory device interface in a communication bus

Dynamic latency map for memory optimization

Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof

Efficient memory usage in systems including volatile and high-density memories

Multiple active vertically aligned cores for three-dimensional chip stack

Multiple active vertically aligned cores for three-dimensional chip stack

Early row address strobe (RAS) precharge

Circuit design for balanced logic stress

Intelligent chip placement within a three-dimensional chip stack

Interconnect solder bumps for die testing

Structure and method of implementing power savings during addressing of DRAM architectures

Device having spare I/O and method of using a device having spare I/O

Setting memory controller driver to memory device termination value in a communication bus

Setting memory device termination in a memory device and memory controller interface in a communication bus

Low power addressing systems

Intelligent chip placement within a three-dimensional chip stack

Design structure of implementing power savings during addressing of DRAM architectures

Production of limited lifetime devices achieved through E-fuses

Fin field effect transistors (FinFETs) and methods for making the same

Circuit design for balanced logic stress

Determining chip burn-in workload using emulated application condition

Donor cores to improve integrated circuit yield

Spider web interconnect topology utilizing multiple port connection

System and memory controller for interruptible memory refresh

Memory device for interruptible memory refresh

FOX BENJAMIN A

Training a memory controller and a memory device using multiple read and write operations

Setting a reference voltage in a memory controller trained to a memory device

Setting controller VREF in a memory controller and memory device interface in a communication bus

Setting controller termination in a memory controller and memory device interface in a communication bus

Setting a reference voltage in a memory controller trained to a memory device

BARTLEY GERALD K

Sorting movable memory hierarchies in a computer system

Structure for multi-level memory architecture with data prioritization