Inventor

DOBUZINSKY DAVID M

US42 patents

⚠️ This page may combine multiple inventors who share the name “DOBUZINSKY DAVID M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DOBUZINSKY DAVID M

IBM

PECVD method of depositing fluorine doped oxide using a fluorine precursor containing a glass-forming element

STI formation in semiconductor device including SOI and bulk silicon regions

Low temperature plasma oxidation process

Method of making TA2 O5 thin film by low temperature ozone plasma annealing (oxidation)

Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates

Low temperature plasma oxidation process

Methods for enhancing trench capacitance and trench capacitor

Thin capacitor dielectric by rapid thermal processing

Vertical SOI trench SONOS cell

Vertical SOI trench SONOS cell

Formation of controlled sublithographic structures

Method of controllably forming a LOCOS oxide layer over a portion of a vertically extending sidewall of a trench extending into a semiconductor substrate

Baffle plate design for decreasing conductance lost during precipitation of polymer precursors in plasma etching chambers

Selective etching process for boron nitride films

Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates

Resist formulation which minimizes blistering during etching

SOI trench capacitor cell incorporating a low-leakage floating body array transistor

Etching openings of different depths using a single mask layer method and structure

Plasma enhanced CVD process for fluorinated silicon nitride films

Self-aligned borderless contacts

Method of making self-aligned borderless contacts

Integrated circuits having reduced stress in metallization

Method for reducing stress in the metallization of an integrated circuit

Fluorinated silicon nitride films

Shallow trench isolation structure compatible with SOI embedded DRAM

Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices

Poly filled substrate contact on SOI structure

STI formation in semiconductor device including SOI and bulk silicon regions

Selective nitride: oxide anisotropic etch process

Embedded DRAM memory cell with additional patterning layer for improved strap formation

Poly filled substrate contact on SOI structure

Vertical SOI trench SONOS cell

SIEMENS AG

Storage node process for deep trench-based DRAM

Application of thin crystalline Si3 N4 liners in shallow trench isolation (STI) structures

Application of thin crystalline Si3 N4 liners in shallow trench isolation (STI) structures

Method and apparatus for preventing formation of black silicon on edges of wafers

TOSHIBA KK

Fabrication process using a multi-layer antireflective layer

Fabrication process using a thin resist

(unassigned)

Fluorinated silicon nitride films

DOBUZINSKY DAVID M

Process for the vapor deposition of polysilanes photoresists

CHENG KANGGUO

Embedded DRAM memory cell with additional patterning layer for improved strap formation

INFINEON TECHNOLOGIES AG

Method to enhance epitaxial regrowth in amorphous silicon contacts