Inventor

LANE CHRISTOPHER F

US70 patents

⚠️ This page may combine multiple inventors who share the name “LANE CHRISTOPHER F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LANE CHRISTOPHER F

ALTERA CORP

Programmable logic device architecture with super-regions having logic regions and a memory region

Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits

Programmable logic array integrated circuit devices with interleaved logic array blocks

Integrated circuits with backside power delivery

Programmable logic device memory array circuit having combinable single-port memory arrays

Circuitry and methods for internal interconnection of programmable logic devices

Programmable logic device circuitry for improving multiplier speed and/or efficiency

Dual-port programmable logic device variable depth and width memory array

Programmable logic array integrated circuit devices

Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits

Programmable logic device with hierarchical interconnection resources

Programmable logic device with expandable-width memory regions

Programmable logic device with hierarchical interconnection resources

Programmable logic array intergrated circuit devices

Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices

Configurable memory structures in a programmable logic device

Programmable logic devices with enhanced multiplexing capabilities

Programmable logic devices with enhanced multiplexing capabilities

Programmable logic array integrated circuit architectures

High density integrated circuit pad structures

Apparatus and methods for power management in integrated circuits

Method of reducing leakage current using sleep transistors in programmable logic device

Method and system for reducing static leakage current in programmable logic devices

Versatile logic element and logic array block

Versatile logic element and logic array block

Efficient arrangement of interconnection resources on programmable logic devices

Routing architecture for a programmable logic device

Programmable logic device with hierarchical interconnection resources

Efficient arrangement of interconnection resources on programmable logic devices

Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits

Programmable logic device circuitry for improving multiplier speed and/or efficiency

Programmable logic device with hierarchical interconnection resources

Programmable logic device memory array circuit having combinable single-port memory arrays

Input/output circuitry for programmable logic devices

Fuse sensing circuit

Method of reducing leakage current using sleep transistors in programmable logic device

Routing architecture for a programmable logic device

Integrated circuit with redundancy

Programmable logic array integrated circuit devices

Multiple size memories in a programmable logic device

Programmable logic devices with enhanced multiplexing capabilities

Programmable logic device with expandable-width memory regions

Versatile logic element and logic array block

I/O configuration and reconfiguration trigger through testing interface

Programmable logic device with hierarchical interconnection resources

Programmable logic device architectures with super-regions having logic regions and memory region

Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices

PLD architecture for flexible placement of IP function blocks

ALTERA CORP SAN JOSE CA

Multifunction memory array in a programmable logic device

(unassigned)

Circuitry and methods for internal interconnection of programmable logic devices