Inventor

MAL JAIN PARAS

US3 patents

⚠️ This page may combine multiple inventors who share the name “MAL JAIN PARAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SYNOPSYS INC

2 patents

US9721057B2Aug 1, 2017

System and method for netlist clock domain crossing verification

SYNOPSYS INC1 citations46

US11238202B2Feb 1, 2022

Verifying glitches in reset path using formal verification and simulation

SYNOPSYS INC0 citations40

ATRENTA INC

1 patent

US7536662B2May 19, 2009

Method for recognizing and verifying FIFO structures in integrated circuit designs

ATRENTA INC11 citations79