Inventor

KANAKASABAPATHY SIVANANDA K

US176 patents

⚠️ This page may combine multiple inventors who share the name “KANAKASABAPATHY SIVANANDA K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KANAKASABAPATHY SIVANANDA K

IBM

Sidewall image transfer process for fin patterning

Self aligned pattern formation post spacer etchback in tight pitch configurations

Fin cut during replacement gate formation

Cutting fins and gates in CMOS devices

Fin cut enabling single diffusion breaks

Asymmetric multi-gate finFET

Metal semiconductor alloy structure for low contact resistance

Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs

Forming a sacrificial liner for dual channel devices

Semiconductor structures including an integrated finFET with deep trench capacitor and methods of manufacture

Registration mark formation during sidewall image transfer process

Self-aligned quadruple patterning process

finFET isolation by selective cyclic etch

Method for integration of magnetic random access memories with improved lithographic alignment to magnetic tunnel junctions

Methods for removing sidewall spacers

Magnetic tunnel junction cap structure and method for forming the same

Hybridization fin reveal for uniform fin reveal depth across different fin pitches

Method for improved alignment of magnetic tunnel junction elements

Semiconductor structures including an integrated FinFET with deep trench capacitor and methods of manufacture

Self aligned pattern formation post spacer etchback in tight pitch configurations

Forming a sacrificial liner for dual channel devices

Semiconductor structures with deep trench capacitor and methods of manufacture

Fin cut during replacement gate formation

Semiconductor structures with deep trench capacitor and methods of manufacture

Semiconductor structures with deep trench capacitor and methods of manufacture

Static random access memory (SRAM) density scaling by using middle of line (MOL) flow

Preventing strained fin relaxation

Method and structure for cut material selection

Stable multiple threshold voltage devices on replacement metal gate CMOS devices

Epitaxial oxide fin segments to prevent strained semiconductor fin end relaxation

FinFET device with channel strain

Structure and method for replacement gate integration with self-aligned contacts

Self aligned conductive lines with relaxed overlay

Pitch scalable active area patterning structure and process for multi-channel finFET technologies

Preventing strained fin relaxation by sealing fin ends

Bulk fin formation with vertical fin sidewall profile

Confined eptaxial growth for continued pitch scaling

FinFET device with channel strain

Trench patterning with block first sidewall image transfer

Structure and method for stress latching in non-planar semiconductor devices

Cut first methodology for double exposure double etch integration

ANDO TAKASHI

FinFET parasitic capacitance reduction using air gap

FinFET parasitic capacitance reduction using air gap

ARNOLD JOHN CHRISTOPHER

Self aligning via patterning

KANAKASABAPATHY SIVANANDA K

Sidewall image transfer using the lithographic stack as the mandrel

BASKER VEERARAGHAVAN S

Spacer as hard mask scheme for in-situ doping in CMOS finFETs

UNIV TEXAS

Ion-Ion plasma processing with bias modulation synchronized to time-modulated discharges

ASSEFA SOLOMON

Method for forming a self-aligned hard mask for contact to a tunnel junction

PONOTH SHOM

Structure for nano-scale metallization and method for fabricating same

HARAN BALASUBRAMANIAN S

Low resistance source and drain extensions for ETSOI