Inventor

PAN PAI HUNG

US110 patents

⚠️ This page may combine multiple inventors who share the name “PAN PAI HUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAN PAI HUNG

MICRON TECHNOLOGY INC

Methods of making implanted structures

Material removal method for forming a structure

Methods, apparatuses and substrate assembly structures for fabricating microelectronic components using mechanical and chemical-mechanical planarization processes

Gate stack with improved sidewall integrity

Semiconductor processing methods of forming a conductive gate and line

Low resistance gate flash memory

Semiconductor structure having a doped conductive layer

Forming a conductive structure in a semiconductor device

Low resistance gate flash memory

Passivation of sidewalls of a word line stack

Semiconductor devices having gate stack with improved sidewall integrity

Semiconductor structure having a doped conductive layer

Material removal method for forming a structure

Material removal method for forming a structure

Ion-assisted oxidation methods and the resulting structures

Method for forming a planar surface over low density field areas on a semiconductor wafer

Ion-assisted oxidation methods and the resulting structures

Forming a conductive structure in a semiconductor device

Integrated circuit container having partially rugged surface

Method of making a field effect transistor having an elevated source and an elevated drain

Method to protect gate stack material during source/drain reoxidation

Method of forming a contact landing pad

Isolation regions and methods of forming isolation regions

Container-shaped bottom electrode for integrated circuit capacitor with partially rugged surface

Method for passivating the sidewalls of a tungsten word line

Method of making a field effect transistor having an elevated source and an elevated drain

Ion-assisted oxidation methods and the resulting structures

Doped silicon diffusion barrier region

Buried bit line memory circuitry

Semiconductor processing methods of forming contact openings, methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random access memory dram circuitry

Semiconductor processing methods of forming contact openings

Methods of forming buried bit line memory circuitry

Shallow trench isolation structure without corner exposure

Method of making a doped silicon diffusion barrier region

Semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening

Isolation regions and methods of forming isolation regions

Method for growing oxide

Method for forming an integrated circuit container having partially rugged surface

Isolation regions and methods of forming isolation regions

Method for growing field oxide to minimize birds&#39; beak length

Field effect transistor

Forming a conductive structure in a semiconductor device

Material removal method for forming a structure

Material removal method for forming a structure

Method for fabricating a structure on a cobalt silicide oxide metalization semiconductor substrate

IBM

Low temperature plasma oxidation process

Method of making single-step trenches using resist fill and recess

Corner protected shallow trench isolation device

Low temperature plasma oxidation process

Oxidation of silicon nitride in semiconductor devices

Method for growing field oxide to minimize birds' beak length