Inventor

THOMAS MAMMEN

US80 patents

⚠️ This page may combine multiple inventors who share the name “THOMAS MAMMEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

THOMAS MAMMEN

ADVANCED MICRO DEVICES INC

Process for formation of trench in integrated circuit structure using isotropic and anisotropic etching

Bipolar and MOS devices fabricated on same integrated circuit substrate

Method of making bipolar and MOS devices on same integrated circuit substrate

Method for making bipolar and CMOS integrated circuit structures

Method of making a planar structure containing MOS and bipolar transistors

Method of making improved lateral polysilicon diode by treating plasma etched sidewalls to remove defects

Double planarization process for multilayer metallization of integrated circuit structures

MOS transistor construction with self aligned silicided contacts to gate, source, and drain regions

Method of forming emitter coupled logic bipolar memory cell using polysilicon Schottky diodes for coupling

Plasma etch process for single-crystal silicon with improved selectivity to silicon dioxide

Via in a planarized dielectric and process for producing same

Method of making a planar MOS device in polysilicon

Method of making a planar polysilicon bipolar device

Fast bipolar transistor for integrated circuit structure and method for forming same

Emitter coupled logic bipolar memory cell

Process for dislocation-free slot isolations in device fabrication

Integrated circuit fabrication process for forming a bipolar transistor having extrinsic base regions

THOMAS MAMMEN

Use of immersive real-time metaverse and avatar and 3-D hologram for medical and veterinary applications using spatially coordinated multi-imager based 3-D imaging

Patient puller

Patient puller

PCI express to PCI express based low latency interconnect scheme for clustering systems

PCI express to PCI express based low latency interconnect scheme for clustering systems

Multi-bit memory technology (MMT) and cells

Location-specific NAND (LS NAND) memory technology and cells

PCI express to PCI express based low latency interconnect scheme for clustering systems

Patient turner-puller

Nvm-aleft-isd-ltsee

Advanced low electrostatic field transistor

ALEFT-ISD-LTSEE{Advanced Low Electrostatic Field Transistor using Implanted S/D and Low Temperature Selective Epitaxial Extension}

TACTICAL FABS INC

High density multichip package with interconnect structure and heatsink

Very high density wafer scale device architecture

Package for an integrated circuit structure

Very high density wafer scale device architecture

Very high density wafer scale device architecture

Very high density wafer scale device architecture

QUICKLOGIC CORP

Electrically programmable interconnect structure having a PECVD amorphous silicon element

Electrically programmable interconnect structure having a PECVD amorphous silicon element

Field programmable gate array having reproducible metal-to-metal amorphous silicon antifuses

Method for fabrication of programmable interconnect structure

Method for fabrication of programmable interconnect structure

(unassigned)

Double poly trenched channel accelerated tunneling electron (DPT-CATE) cell, for memory applications

Channel accelerated tunneling electron cell, with a select region incorporated, for high density low power applications

Channel accelerated carrier tunneling-(CACT) method for programming memories

ALTERA CORP

Method and apparatus for a network processor having an architecture that supports burst writes and/or reads

Apparatus and method for queuing flow management between input, intermediate and output queues

Packet classification method

MADATHILPARAMBIL GEORGE GEORGE

System for avoiding layer 2 network congestion

Delaying layer 2 frame transmission

Data link frame reordering

NIF/T LLC

FFT-dram