Inventor

KURAKAZU KEIICHI

JP34 patents

⚠️ This page may combine multiple inventors who share the name “KURAKAZU KEIICHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KURAKAZU KEIICHI

HITACHI LTD

Microcomputer having multiple bus structure coupling CPU to other processing elements

Microcomputer having 16 bit fixed length instruction format

Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory

Microcomputer system with at least first and second microcomputers each operable in master and slave modes with configurable bus access control terminals and bus use priority controller

Single-chip microcomputer synchronously controlling external synchronous memory responsive to memory clock signal and clock enable signal

Data processing system for development of outline fonts

Data processing system

Instruction format for program control type data processing systems

Processing system with microcomputers each operable in master and slave modes using configurable bus access control terminals and bus use priority signals

Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation

Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals

RISC system with instructions which include register area and displacement portions for accessing data stored in registers during processing

Data processing system having multiple register management for call and return operations

Data processor

RISC system performing calls and returns without saving or restoring window pointers and delaying saving until multi-register areas are filled

Microprocessor

Data processor and data processing system

Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word

Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation

Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word

Division circuit and the division method thereof

Data processor with fast break in program execution by selectively processing either external control signal or external interrupt

Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements

Bus error processing system having direct bus master/CPU communication

Microcomputer and dividing circuit

Microcomputer having variable bit width area for displacement

Data processor providing fast break in program execution

Data processor providing fast break in program execution

RISC system capable of performing calls and returns without advancing or restoring window pointers

Microcomputer with synchronized data transfer

Data processing system

Data processing system

Branch instruction having different field lengths for unconditional and conditional displacements

RENESAS TECH CORP

Microcomputer and dividing circuit