Inventor

LUICK DAVID ARNOLD

US53 patents

⚠️ This page may combine multiple inventors who share the name “LUICK DAVID ARNOLD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LUICK DAVID ARNOLD

IBM

Method and apparatus to eliminate processor core hot spots

Branch history cache

Circuit arrangement and method of speculative instruction execution utilizing instruction history caching

Compression architecture for system memory application

Very long instruction word (VLIW) computer having efficient instruction code format

Multiprocessor cache coherence directed by combined local and global tables

Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cache

Multiple parallel pipeline processor having self-repairing capability

Multiple processor core device having shareable functional units for self-repairing capability

Apparatus and method for pre-fetching data to cached memory using persistent historical page table data

Apparatus and method for pre-fetching page data using segment table data

Scheme to encode predicted values into an instruction stream/cache without additional bits/area

Partition of on-chip memory buffer for cache

Scheme to partition a large lookaside buffer into an L2 cache array

Multi-ported and interleaved cache memory supporting multiple simultaneous accesses thereto

Multiple port high speed register file with interleaved write ports for use with very long instruction word (vlin) and n-way superscaler processors

Instruction group formation and mechanism for SMT dispatch

Reordering of memory reference operations and conflict resolution via rollback in a multiprocessing environment

Method and apparatus to select the next instruction in a superscalar or a very long instruction word computer having N-way branching

Structure for a single shared instruction predecoder for supporting multiple processors

In situ register state error recovery and restart mechanism

Load misaligned vector with permute and mask insert

Method and apparatus for accessing a split cache directory

Method and apparatus for transferring control in a computer system with dynamic compilation capability

Wide adder with critical path of three gates

Computer system architecture for a processor connected to a high speed bus transceiver

Reproducing errors via inhibit switches

High frequency compound instruction mechanism and method for a compare operation in an arithmetic logic unit

Result forwarding of either input operand to same operand input to reduce forwarding path

History-based carry predictor for data cache address generation

Method and apparatus for detecting pipeline address conflict using compare of byte addresses

System for restoring register data in a pipelined data processing system using latch feedback assemblies

System for restoring register data in a pipelined data processing system using latch feedback assemblies

System for restoring register data in a pipelined data processing system using register file save/restore mechanism

Error detection during processor idle cycles

Design structure for single hot forward interconnect scheme for delayed execution pipelines

Method and apparatus for accessing a cache with an effective address

Single hot forward interconnect scheme for delayed execution pipelines

Method and apparatus for multiple load instruction execution

Single cycle context switching by swapping a primary latch value and a selected secondary latch value in a register file

Adaptive runtime repairable entry register file

Fast forwarding ALU

Transmission error checking in result forwarding

Method and apparatus for detecting pipeline address conflict using parallel compares of multiple real addresses

Zero delay data cache effective address generation

Instruction pair detection and pseudo ports for cache array

Register file bit and method for fast context switch

LUICK DAVID ARNOLD

Scalar precision float implementation on the “W” lane of vector unit

Store misaligned vector with permute

EICKEMEYER RICHARD JAMES

Multithreaded processor and method for switching threads by swapping instructions between buffers while pausing execution