Inventor

BELL SCOTT A

US80 patents

⚠️ This page may combine multiple inventors who share the name “BELL SCOTT A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BELL SCOTT A

ADVANCED MICRO DEVICES INC

Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning

Use of amorphous carbon hard mask for gate patterning to eliminate requirement of poly re-oxidation

Planar finFET patterning using amorphous carbon

Bi-layer trim etch process to form integrated circuit gate structures

Use of silicon containing imaging layer to define sub-resolution gate structures

Method of forming sub-lithographic spaces between polysilicon lines

RELACS process to double the frequency or pitch of small feature formation

Method using a thin resist mask for dual damascene stop layer etch

Ultra-thin resist and nitride/oxide hard mask for metal etch

Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance

Method of using amorphous carbon film as a sacrificial layer in replacement gate integration processes

Thin resist with transition metal hard mask for via etch application

Thin resist with nitride hard mask for gate etch application

Thin resist with amorphous silicon hard mask for via etch application

Method of etching a polysilicon pattern

Hardmask trim process

Ion implantation to modulate amorphous carbon stress

Antireflective bi-layer hardmask including a densified amorphous carbon layer

CVD organic polymer film for advanced gate patterning

Method for defect reduction and enhanced control over critical dimensions and profiles in semiconductor devices

Flash memory with controlled wordline width

Method of pinhole decoration and detection

Multilayer anti-reflective coating process for integrated circuit fabrication

In-situ process for monitoring lateral photoresist etching

Plasma emission detection during lateral processing of photoresist mask

Ultra-thin resist and SiON/oxide hard mask for metal etch

Ultra-thin resist and barrier metal/oxide hard mask for metal etch

Ultra-thin resist and oxide/nitride hard mask for metal etch

Thin resist with transition metal hard mask for via etch application

Ultra-thin resist and silicon/oxide hard mask for metal etch

Method for transferring patterns created by lithography

Thin resist with nitride hard mask for via etch application

Gate pattern formation using a BARC as a hardmask

Use of multilayer amorphous carbon ARC stack to eliminate line warpage phenomenon

Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication

Silicon oxime spacer for preventing over-etching during local interconnect formation

Gate pattern formation using a bottom anti-reflective coating

Two mask photoresist exposure pattern for dense and isolated regions

Controlled linewidth reduction during gate pattern formation using an SiON BARC

Controlled linewidth reduction during gate pattern formation using a spin-on barc

Heat treating nitrogen implanted gate electrode layer for improved gate electrode etch profile

Method for forming integrated circuit

System and method using in situ scatterometry to detect photoresist pattern integrity during the photolithography process

Method of using amorphous carbon to prevent resist poisoning

Method of strengthening photoresist to prevent pattern collapse

Two mask photoresist exposure pattern for dense and isolated regions

Patterning with rigid organic under-layer

Method for semiconductor gate line dimension reduction

Method for reducing gate line deformation and reducing gate line widths in semiconductor devices

(unassigned)

Etch bias distribution across semiconductor wafer