Inventor
FOREMAN ERIC
US9 patents
Patents
9 patentsUS10037402B1Jul 31, 2018
Parameter collapsing and corner reduction in an integrated circuit
IBM5 citations80
US11074386B2Jul 27, 2021
Method of parameter creation
IBM0 citations60
US10409938B2Sep 10, 2019
Method of parameter creation
IBM1 citations60
US11720732B2Aug 8, 2023
Determining a blended timing constraint that satisfies multiple timing constraints and user-selected specifications
IBM1 citations52
US10546095B2Jan 28, 2020
Parameter collapsing and corner reduction in an integrated circuit
IBM0 citations48
US10354047B2Jul 16, 2019
Parameter collapsing and corner reduction in an integrated circuit
IBM0 citations48
US10296704B2May 21, 2019
Parameter collapsing and corner reduction in an integrated circuit
IBM0 citations48
US10747925B1Aug 18, 2020
Variable accuracy incremental timing analysis
IBM0 citations39
US10691853B2Jun 23, 2020
Superposition of canonical timing value representations in statistical static timing analysis
IBM0 citations33