Inventor
APPU ABHISHEK
US29 patents
Patents
29 patentsUS11620256B2Apr 4, 2023
Systems and methods for improving cache efficiency and utilization
INTEL CORP36 citations97
US11113784B2Sep 7, 2021
Sparse optimizations for a matrix accelerator architecture
INTEL CORP46 citations97
US12079155B2Sep 3, 2024
Graphics processor operation scheduling for deterministic latency
INTEL CORP6 citations93
US12182035B2Dec 31, 2024
Systems and methods for cache optimization
INTEL CORP6 citations86
US11842423B2Dec 12, 2023
Dot product operations on sparse matrix elements
INTEL CORP4 citations86
US12210477B2Jan 28, 2025
Systems and methods for improving cache efficiency and utilization
INTEL CORP2 citations85
US11954062B2Apr 9, 2024
Dynamic memory reconfiguration
INTEL CORP3 citations85
US11755501B2Sep 12, 2023
Efficient data sharing for graphics data processing operations
INTEL CORP9 citations85
US11676239B2Jun 13, 2023
Sparse optimizations for a matrix accelerator architecture
INTEL CORP10 citations85
US12141094B2Nov 12, 2024
Systolic disaggregation within a matrix accelerator architecture
INTEL CORP2 citations84
US11995029B2May 28, 2024
Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration
INTEL CORP2 citations84
US10424107B2Sep 24, 2019
Hierarchical depth buffer back annotaton
INTEL CORP5 citations81
US12124383B2Oct 22, 2024
Systems and methods for cache optimization
INTEL CORP3 citations75
US12056059B2Aug 6, 2024
Systems and methods for cache optimization
INTEL CORP3 citations75
US12561276B2Feb 24, 2026
Systems and methods for updating memory side caches in a multi-GPU configuration
INTEL CORP0 citations73
US12386779B2Aug 12, 2025
Dynamic memory reconfiguration
INTEL CORP0 citations73
US12032496B2Jul 9, 2024
Efficient data sharing for graphics data processing operations
INTEL CORP1 citations72
US10402224B2Sep 3, 2019
Microcontroller-based flexible thread scheduling launching in computing environments
INTEL CORP2 citations72
US12541908B2Feb 3, 2026
Apparatus and method for throttling a ray tracing pipeline
INTEL CORP0 citations63
US11915357B2Feb 27, 2024
Apparatus and method for throttling a ray tracing pipeline
INTEL CORP0 citations63
US11631198B2Apr 18, 2023
Targeted mapping of graphical data for compression
INTEL CORP0 citations63
US12306771B2May 20, 2025
Efficient data sharing for graphics data processing operations
INTEL CORP0 citations62
US12293431B2May 6, 2025
Sparse optimizations for a matrix accelerator architecture
INTEL CORP0 citations62
US12198222B2Jan 14, 2025
Architecture for block sparse operations on a systolic array
INTEL CORP0 citations62
US11175949B2Nov 16, 2021
Microcontroller-based flexible thread scheduling launching in computing environments
INTEL CORP0 citations62
US11615584B2Mar 28, 2023
Hierarchical depth buffer back annotation
INTEL CORP0 citations59
US11080925B2Aug 3, 2021
Hierarchical depth buffer back annotation
INTEL CORP0 citations59
US11580361B2Feb 14, 2023
Neural network training mechanism
INTEL CORP0 citations52
US11194722B2Dec 7, 2021
Apparatus and method for improved cache utilization and efficiency on a many core processor
INTEL CORP0 citations45