Inventor
POMERENE JAMES H
US21 patents
Patents
21 patentsUS4903196AFeb 20, 1990
Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor
IBM191 citations99
US5434985AJul 18, 1995
Simultaneous prediction of multiple branches for superscalar processing
IBM139 citations98
US4991080AFeb 5, 1991
Pipeline processing apparatus for executing instructions in three streams, including branch stream pre-execution processor for pre-executing conditional branch instructions
IBM122 citations98
US5353421AOct 4, 1994
Multi-prediction branch prediction mechanism
IBM109 citations96
US5210831AMay 11, 1993
Methods and apparatus for insulating a branch prediction mechanism from data dependent branch table updates that result from variable test operand locations
IBM65 citations96
US5155831AOct 13, 1992
Data processing system with fast queue store interposed between store-through caches and a main memory
IBM102 citations96
US4807110AFeb 21, 1989
Prefetching system for a cache having a second directory for sequentially accessed blocks
IBM106 citations96
US4774654ASep 27, 1988
Apparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depending upon state of replacing bit in the low speed memory
IBM59 citations96
US4437149AMar 13, 1984
Cache memory architecture with decoding
IBM74 citations96
US4295193AOct 13, 1981
Machine for multiple instruction execution
IBM113 citations96
US4991090AFeb 5, 1991
Posting out-of-sequence fetches
IBM61 citations95
US4943908AJul 24, 1990
Multiple branch analyzer for prefetching cache lines
IBM87 citations95
US4763245AAug 9, 1988
Branch prediction mechanism in which a branch history table is updated using an operand sensitive branch table
IBM62 citations95
US4679141AJul 7, 1987
Pageable branch history table
IBM107 citations95
US4823259AApr 18, 1989
High speed buffer store arrangement for quick wide transfer of data
IBM66 citations94
US5297281AMar 22, 1994
Multiple sequence processor system
IBM30 citations92
US5291442AMar 1, 1994
Method and apparatus for dynamic cache line sectoring in multiprocessor systems
IBM53 citations92
US5276882AJan 4, 1994
Subroutine return through branch history table
IBM47 citations92
US5233702AAug 3, 1993
Cache miss facility with stored sequences for data fetching
IBM32 citations92
US5197139AMar 23, 1993
Cache management for multi-processor systems utilizing bulk cross-invalidate
IBM52 citations92
US5584002ADec 10, 1996
Cache remapping using synonym classes
IBM16 citations73