Inventor

CHANG KEH-JENG

US48 patents

⚠️ This page may combine multiple inventors who share the name “CHANG KEH-JENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG KEH-JENG

TAIWAN SEMICONDUCTOR MFG CO LTD

Power rails for stacked semiconductor device

Laser interference fringe control for higher EUV light source and EUV throughput

Field effect transistor with negative capacitance dielectric structures

Laser interference fringe control for higher EUV light source and EUV throughput

Independent control of stacked semiconductor device

Field effect transistors with negative capacitance layers

Radical-activated etching of metal oxides

Laser interference fringe control for higher EUV light source and EUV throughput

Field effect transistor with negative capacitance dieletric structures

Memory devices, semiconductor devices, and methods of operating a memory device

Semiconductor process technology assessment

Semiconductor process technology assessment

Plasma-assisted etching of metal oxides

Grid structures of ion beam etching (IBE) systems

Method for fabricating an integrated circuit comprising devices on opposing sides of a substrate

Power rails for stacked semiconductor device

Method of manufacturing integrated circuit

Radical-activated etching of metal oxides

Field effect transistor with negative capacitance dielectric structures

Independent control of stacked semiconductor device

Memory devices, semiconductor devices, and methods of operations a memory device

Nanostructured channel regions for semiconductor devices

Heat dissipation in semiconductor packages and methods of forming same

Field effect transistors with negative capacitance layers

Grid structures of ion beam etching (IBE) systems

Independent control of stacked semiconductor device

Nanostructured channel regions for semiconductor devices

Power rails for stacked semiconductor device

Field effect transistor with negative capacitance dielectric structures

Field effect transistors with negative capacitance layers

Heat dissipation in semiconductor packages and methods of forming same

Plasma-assisted etching of metal oxides

Semiconductor process technology assessment

Gate structures for semiconductor devices

Interposer with capacitors

Interferometer systems and methods for real time etch process compensation control

SEQUENCE DESIGN INC

Method and system for extraction of parasitic interconnect impedance including inductance

Method and system for extraction of parasitic interconnect impedance including inductance

Methods for determining on-chip interconnect process parameters

Methods for determining on-chip interconnect process parameters

Method for determining on-chip sheet resistivity

Method for modeling a conductive semiconductor substrate

FREQUENCY TECHNOLOGY INC

System and method for extracting parasitic impedance from an integrated circuit layout

Methods for determining on-chip interconnect process parameters

TAIWAN SEMICONDUCTOR MFG

Accurate capacitance measurement for ultra large scale integrated circuits

Accurate capacitance measurement for ultra large scale integrated circuits

HEWLETT PACKARD CO

Computer-aided design methods and apparatus for multilevel interconnect technologies

DOONG YIH-YUH

Accurate capacitance measurement for ultra large scale integrated circuits