Inventor

FISCUS TIMOTHY E

US14 patents

⚠️ This page may combine multiple inventors who share the name “FISCUS TIMOTHY E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CYPRESS SEMICONDUCTOR CORP

7 patents

US6628154B2Sep 30, 2003

Digitally controlled analog delay locked loop (DLL)

CYPRESS SEMICONDUCTOR CORP109 citations97

US7057960B1Jun 6, 2006

Method and architecture for reducing the power consumption for memory devices in refresh operations

CYPRESS SEMICONDUCTOR CORP80 citations96

US6628558B2Sep 30, 2003

Proportional to temperature voltage generator

CYPRESS SEMICONDUCTOR CORP72 citations96

US6618314B1Sep 9, 2003

Method and architecture for reducing the power consumption for memory devices in refresh operations

CYPRESS SEMICONDUCTOR CORP49 citations95

US6901022B2May 31, 2005

IBM

4 patents

US6492852B2Dec 10, 2002

Pre-divider architecture for low power in a digital delay locked loop

IBM82 citations97

US6529993B1Mar 4, 2003

Data and data strobe circuits and operating protocol for double data rate memories

IBM60 citations94

US6708298B2Mar 16, 2004

Method for guaranteeing a minimum data strobe valid window and a minimum data valid window for DDR memory devices

IBM13 citations81

US6658604B1Dec 2, 2003

Method for testing and guaranteeing that skew between two signals meets predetermined criteria

IBM16 citations81

INTEL CORP

3 patents

US5994939ANov 30, 1999

Variable delay cell with a self-biasing load

INTEL CORP98 citations98

US6255873B1Jul 3, 2001

Setting the common mode level of a differential charge pump output

INTEL CORP25 citations92

US6184732B1Feb 6, 2001

Setting the common mode level of a differential charge pump output

INTEL CORP14 citations74

FISCUS TIMOTHY E

CYPRESS SEMICONDUCTOR CORP

Digitally controlled analog delay locked loop (DLL)

Method and architecture for reducing the power consumption for memory devices in refresh operations

Proportional to temperature voltage generator

Method and architecture for reducing the power consumption for memory devices in refresh operations

Proportional to temperature voltage generator

Method and architecture for self-clocking digital delay locked loop

Method and architecture for refreshing a 1T memory proportional to temperature

IBM

Pre-divider architecture for low power in a digital delay locked loop

Data and data strobe circuits and operating protocol for double data rate memories

Method for guaranteeing a minimum data strobe valid window and a minimum data valid window for DDR memory devices

Method for testing and guaranteeing that skew between two signals meets predetermined criteria

INTEL CORP

Variable delay cell with a self-biasing load

Setting the common mode level of a differential charge pump output

Setting the common mode level of a differential charge pump output