Inventor
CHAN YI-LING
TW6 patents
Patents
6 patentsUS6518105B1Feb 11, 2003
High performance PD SOI tunneling-biased MOSFET
TAIWAN SEMICONDUCTOR MFG214 citations98
US6784071B2Aug 31, 2004
Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement
TAIWAN SEMICONDUCTOR MFG58 citations95
US7122412B2Oct 17, 2006
Method of fabricating a necked FINFET device
TAIWAN SEMICONDUCTOR MFG33 citations92
US6673683B1Jan 6, 2004
Damascene gate electrode method for fabricating field effect transistor (FET) device with ion implanted lightly doped extension regions
TAIWAN SEMICONDUCTOR MFG42 citations92
US6674130B2Jan 6, 2004
High performance PD SOI tunneling-biased MOSFET
TAIWAN SEMICONDUCTOR MFG3 citations62
US6800516B2Oct 5, 2004
Electrostatic discharge device protection structure
TAIWAN SEMICONDUCTOR MFG1 citations51