Inventor

YOSHIMURA MASAYOSHI

JP20 patents

⚠️ This page may combine multiple inventors who share the name “YOSHIMURA MASAYOSHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YOSHIMURA MASAYOSHI

HITACHI LTD

Single in-line high power resin-packaged semiconductor device having an improved heat dissipator

Level conversion circuitry for a semiconductor integrated circuit utilizing bis CMOS circuit elements

Etching method for flattening a silicon substrate utilizing an anisotropic alkali etchant

Resistance element for semiconductor integrated circuit

Level conversion circuitry for a semiconductor integrated circuit

Semiconductor integrated circuit with a bi-MOS input circuit for providing input signals to an internal logic block

Transistor circuit for deep saturation prevention

High-breakdown-voltage resistance element for integrated circuit with a plurality of multilayer, overlapping electrodes

Bicmos gate array

Level conversion circuitry for a semiconductor integrated circuit

Transistor with base/emitter encirclement configuration

High-breakdown-voltage semiconductor device

Level conversion circuitry for a semiconductor integrated circuit

BiCMOS tri-state output driver

MATSUSHITA ELECTRIC INDUSTRIAL CO LTD

Semiconductor device having a device for testing the semiconductor

Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device

Semiconductor integrated circuit and testing method for the same

Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device

Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device

Method of design for testability, method of design for integrated circuits and integrated circuits