Inventor
PEDRAM MASSOUD
US12 patents
⚠️ This page may combine multiple inventors who share the name “PEDRAM MASSOUD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
FUJITSU LTD
8 patentsUS7573775B2Aug 11, 2009
Setting threshold voltages of cells in a memory block to reduce leakage in the memory block
FUJITSU LTD15 citations82
US7400175B2Jul 15, 2008
Recycling charge to reduce energy consumption during mode transition in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits
FUJITSU LTD16 citations80
US6834335B2Dec 21, 2004
System and method for reducing transitions on address buses
FUJITSU LTD8 citations71
US7447101B2Nov 4, 2008
PG-gated data retention technique for reducing leakage in memory cells
FUJITSU LTD6 citations60
US7236107B2Jun 26, 2007
System and method for identifying optimal encoding for a given trace
FUJITSU LTD2 citations60
US6813700B2Nov 2, 2004
Reduction of bus switching activity using an encoder and decoder
FUJITSU LTD5 citations60
US7834684B2Nov 16, 2010
Sizing and placement of charge recycling (CR) transistors in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits
FUJITSU LTD4 citations59
US7613942B2Nov 3, 2009
Power mode transition in multi-threshold complementary metal oxide semiconductor (MTCMOS) circuits
FUJITSU LTD4 citations56
UNIV SOUTHERN CALIFORNIA
3 patentsUS10707873B2Jul 7, 2020
Superconducting magnetic field programmable gate array
UNIV SOUTHERN CALIFORNIA3 citations66
US11303281B2Apr 12, 2022
Efficient pipelined architecture for superconducting single flux quantum logic circuits utilizing dual clocks
UNIV SOUTHERN CALIFORNIA0 citations51
US6907511B2Jun 14, 2005
Reducing transitions on address buses using instruction-set-aware system and method
UNIV SOUTHERN CALIFORNIA1 citations50