Inventor
HSU LOUIS L
US281 patents
Patents
50 patentsUS6556477B2Apr 29, 2003
Integrated chip having SRAM, DRAM and flash memory and method for fabricating the same
IBM232 citations99
US6552398B2Apr 22, 2003
T-Ram array having a planar cell structure and method for fabricating the same
IBM218 citations99
US6337513B1Jan 8, 2002
Chip packaging system and method using deposited diamond film
IBM188 citations99
US6323554B1Nov 27, 2001
Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD
IBM117 citations99
US5784311AJul 21, 1998
Two-device memory cell on SOI for merged logic and memory applications
IBM278 citations99
US5585673ADec 17, 1996
Refractory metal capped low resistivity metal conductor lines and vias
IBM174 citations99
US5391510AFeb 21, 1995
Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps
IBM394 citations99
US5300813AApr 5, 1994
Refractory metal capped low resistivity metal conductor lines and vias
IBM155 citations99
US7170164B2Jan 30, 2007
Cooling system for a semiconductor device and method of fabricating same
IBM91 citations98
US7052937B2May 30, 2006
Method and structure for providing improved thermal conduction for silicon semiconductor devices
IBM64 citations98
US7029951B2Apr 18, 2006
Cooling system for a semiconductor device and method of fabricating same
IBM97 citations98
US6876250B2Apr 5, 2005
Low-power band-gap reference and temperature sensor circuit
IBM94 citations98
US6825534B2Nov 30, 2004
Semiconductor device on a combination bulk silicon and silicon-on-insulator (SOI) substrate
IBM113 citations98
US6777761B2Aug 17, 2004
Semiconductor chip using both polysilicon and metal gate devices
IBM72 citations98
US6697909B1Feb 24, 2004
Method and apparatus for performing data access and refresh operations in different sub-arrays of a DRAM cache memory
IBM81 citations98
US6670234B2Dec 30, 2003
Method of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereof
IBM115 citations98
US6611033B2Aug 26, 2003
Micromachined electromechanical (MEM) random access memory array and method of making same
IBM90 citations98
US6549450B1Apr 15, 2003
Method and system for improving the performance on SOI memory arrays in an SRAM architecture system
IBM226 citations98
US6541815B1Apr 1, 2003
High-density dual-cell flash memory structure
IBM117 citations98
US6531911B1Mar 11, 2003
Low-power band-gap reference and temperature sensor circuit
IBM103 citations98
US6411157B1Jun 25, 2002
Self-refresh on-chip voltage generator
IBM99 citations98
US6358791B1Mar 19, 2002
Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby
IBM99 citations98
US5774411AJun 30, 1998
Methods to enhance SOI SRAM cell stability
IBM206 citations98
US5675164AOct 7, 1997
High performance multi-mesa field effect transistor
IBM119 citations98
US5234535AAug 10, 1993
Method of producing a thin silicon-on-insulator layer
IBM197 citations98
US6245613B1Jun 12, 2001
Field effect transistor having a floating gate
IBM190 citations97
US6144054ANov 7, 2000
DRAM cell having an annular signal transfer region
IBM106 citations97
US6097056AAug 1, 2000
Field effect transistor having a floating gate
IBM166 citations97
US5889328AMar 30, 1999
Refractory metal capped low resistivity metal conductor lines and vias
IBM78 citations97
US5532089AJul 2, 1996
Simplified fabrication methods for rim phase-shift masks
IBM105 citations97
US5516721AMay 14, 1996
Isolation structure using liquid phase oxide deposition
IBM126 citations97
US5405795AApr 11, 1995
Method of forming a SOI transistor having a self-aligned body contact
IBM110 citations97
US5403779AApr 4, 1995
Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD
IBM103 citations97
US7138685B2Nov 21, 2006
Vertical MOSFET SRAM cell
IBM54 citations96
US6911375B2Jun 28, 2005
Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
IBM64 citations96
US6720595B2Apr 13, 2004
Three-dimensional island pixel photo-sensor
IBM59 citations96
US6649959B2Nov 18, 2003
Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby
IBM59 citations96
US6627924B2Sep 30, 2003
Memory system capable of operating at high temperatures and method for fabricating the same
IBM48 citations96
US6570207B2May 27, 2003
Structure and method for creating vertical capacitor and anti-fuse in DRAM process employing vertical array device cell complex
IBM65 citations96
US6507237B2Jan 14, 2003
Low-power DC voltage generator system
IBM44 citations96
US6492662B2Dec 10, 2002
T-RAM structure having dual vertical devices and method for fabricating the same
IBM75 citations96
US6437623B1Aug 20, 2002
Data retention registers
IBM64 citations96
US6337595B1Jan 8, 2002
Low-power DC voltage generator system
IBM52 citations96
US6255712B1Jul 3, 2001
Semi-sacrificial diamond for air dielectric formation
IBM61 citations96
US6214653B1Apr 10, 2001
Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate
IBM72 citations96
US6147402ANov 14, 2000
Refractory metal capped low resistivity metal conductor lines and vias
IBM34 citations96
US5976975ANov 2, 1999
Refractory metal capped low resistivity metal conductor lines and vias
IBM51 citations96
US5770875AJun 23, 1998
Large value capacitor for SOI
IBM64 citations96
US5759907AJun 2, 1998
Method of making large value capacitor for SOI
IBM80 citations96
US5426330AJun 20, 1995
Refractory metal capped low resistivity metal conductor lines and vias
IBM64 citations96
Showing the top 50 of 281 patents by PatentIndex Score.