Inventor

MORZANO CHRISTOPHER K

US50 patents

⚠️ This page may combine multiple inventors who share the name “MORZANO CHRISTOPHER K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MORZANO CHRISTOPHER K

MICRON TECHNOLOGY INC

DDR II write data capture calibration

Memory device with synchronized output path

Self-queuing serial output port

Data strobe synchronization circuit and method for double data rate, multi-bit writes

Read/write timing calibration of a memory array using a row or a redundant row

Compensation for a delay locked loop

Compensation for a delay locked loop

Delay lock loops, signal locking methods and methods of implementing delay lock loops

Data compression test mode independent of redundancy

Programmable bandwidth I/O port and a communication interface using the same port having a plurality of serial access memories capable of being configured for a variety of protocols

Apparatuses having stacked devices and methods of connecting dice stacks

DDR II write data capture calibration

Write address synchronization useful for a DDR prefetch SDRAM

Method and circuit for off chip driver control, and memory device using same

Memory array decoder

High frequency range four bit prefetch output data path

High frequency range four bit prefetch output data path

Write data masking for higher speed DRAMs

Differential input buffer bias circuit

Method and apparatus for testing cells in a memory device with compressed data and for replacing defective cells

Multiport serial access self-queuing memory switch

High speed programmable counter

Data strobe synchronization circuit and method for double data rate, multi-bit writes

Method and apparatus for converting parallel data to serial data in high speed applications

Apparatus and method for adjusting clock skew

Method and apparatus for converting parallel data to serial data in high speed applications

Method and circuit for off chip driver control, and memory device using same

DDR II write data capture calibration

Memory array decoder

Write address synchronization useful for a DDR prefetch SDRAM

Solution to DQS postamble ringing problem in memory chips

System and technique to reduce cycle time by performing column redundancy checks during a delay to accommodate variations in timing of a data strobe signal

Write data masking for higher speed drams

System and method to reduce cycle time by performing column redundancy checks during a delay to accommodate variations in timing of a data strobe signal

Voltage differential sensing circuit and methods of using same

High speed programmable counter

Pre-sense gut node amplification in sense amplifier

Synchronous command-based write recovery time auto-precharge control

Data strobe synchronization circuit and method for double data rate, multi-bit writes

Apparatus and method for adjusting clock skew

Voltage differential sensing circuit and methods of using same

Voltage differential sensing circuit and methods of using same

High speed programmable counter

Memory array decoder

Memory array decoder

High speed programmable counter

ROUND ROCK RES LLC

Parallel-to-serial data sort device

Method and circuit for off chip driver control, and memory device using same

KEETH BRENT

Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same

WONG VICTOR

Synchronous command-based write recovery time auto-precharge control