Inventor

KECKLER STEPHEN W

US29 patents

⚠️ This page may combine multiple inventors who share the name “KECKLER STEPHEN W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KECKLER STEPHEN W

NVIDIA CORP

Hierarchical network for stacked memory system

Hierarchical network for stacked memory system

Application partitioning for locality in a stacked memory system

Adversarial scenarios for safety testing of autonomous vehicles

Tensor-based driving scenario characterization

Efficient neural network accelerator dataflows

System and methods for hardware-software cooperative pipeline error detection

System and methods for hardware-software cooperative pipeline error detection

System and methods for hardware-software cooperative pipeline error detection

Efficient neural network accelerator dataflows

Deep neural network accelerator with fine-grained parallelism discovery

Adversarial scenarios for safety testing of autonomous vehicles

Scalable multi-die deep learning system

Optimizing software-directed instruction replication for GPU error detection

UNIV TEXAS

Non-uniform cache apparatus, systems, and methods

Computing nodes for executing groups of instructions

Combined branch target and predicate prediction

Method and apparatus for congestion-aware routing in a computer interconnection network

MASSACHUSETTS INST TECHNOLOGY

Multiprocessor coupling system with integrated compile and run time scheduling for parallelism

Memory system with global address translation

Memory system including guarded pointers

BURGER DOUGLAS C

Unordered load/store queue

Combined branch target and predicate prediction for instruction blocks

Dynamically composing processor cores to form logical processors

BURGER DOUG

Method, system and computer-accessible medium for providing a distributed predicate prediction

Control-flow prediction using multiple independent predictors

Data multicasting with router replication and target instruction identification in a distributed multi-core processing architecture

GRATZ PAUL

Method and apparatus for congestion-aware routing in a computer interconnection network

KECKLER STEPHEN W

Scalable bus-based on-chip interconnection networks