Inventor
CRETA KENNETH C
US36 patents
⚠️ This page may combine multiple inventors who share the name “CRETA KENNETH C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
32 patentsUS6216247B1Apr 10, 2001
32-bit mode for a 64-bit ECC capable memory subsystem
INTEL CORP179 citations98
US6681292B2Jan 20, 2004
Distributed read and write caching implementation for optimized input/output applications
INTEL CORP294 citations97
US7210000B2Apr 24, 2007
Transmitting peer-to-peer transactions through a coherent interface
INTEL CORP51 citations96
US7184399B2Feb 27, 2007
Method for handling completion packets with a non-successful completion status
INTEL CORP25 citations93
US6978351B2Dec 20, 2005
Method and system to improve prefetching operations
INTEL CORP27 citations93
US7165131B2Jan 16, 2007
Separating transactions into different virtual channels
INTEL CORP25 citations92
US7124252B1Oct 17, 2006
Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system
INTEL CORP28 citations92
US6088762AJul 11, 2000
Power failure mode for a memory controller
INTEL CORP44 citations92
US9575895B2Feb 21, 2017
Providing common caching agent for core and integrated input/output (IO) module
INTEL CORP5 citations84
US7206865B2Apr 17, 2007
Apparatus and method for combining writes to I/O
INTEL CORP15 citations84
US7089362B2Aug 8, 2006
Cache memory eviction policy for combining write transactions
INTEL CORP11 citations84
US6859864B2Feb 22, 2005
Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache line
INTEL CORP14 citations84
US6694383B2Feb 17, 2004
Handling service requests
INTEL CORP16 citations84
US7353301B2Apr 1, 2008
Methodology and apparatus for implementing write combining
INTEL CORP10 citations83
US8046539B2Oct 25, 2011
Method and apparatus for the synchronization of distributed caches
INTEL CORP9 citations82
US7996572B2Aug 9, 2011
Multi-node chipset lock flow with peer-to-peer non-posted I/O requests
INTEL CORP16 citations82
US7546422B2Jun 9, 2009
Method and apparatus for the synchronization of distributed caches
INTEL CORP12 citations82
US6801976B2Oct 5, 2004
Mechanism for preserving producer-consumer ordering across an unordered interface
INTEL CORP17 citations82
US6915365B2Jul 5, 2005
Mechanism for PCI I/O-initiated configuration cycles
INTEL CORP18 citations77
US8006017B2Aug 23, 2011
Stream priority
INTEL CORP4 citations74
US7676603B2Mar 9, 2010
Write combining protocol between processors and chipsets
INTEL CORP6 citations74
US10915468B2Feb 9, 2021
Sharing memory and I/O services between nodes
INTEL CORP4 citations72
US7162546B2Jan 9, 2007
Reordering unrelated transactions from an ordered interface
INTEL CORP9 citations72
US7000041B2Feb 14, 2006
Method and an apparatus to efficiently handle read completions that satisfy a read request
INTEL CORP6 citations68
US8347011B2Jan 1, 2013
Stream priority
INTEL CORP4 citations63
US7363393B2Apr 22, 2008
Chipset feature detection and configuration by an I/O device
INTEL CORP3 citations63
US6976129B2Dec 13, 2005
Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture
INTEL CORP5 citations63
US12517846B2Jan 6, 2026
Sharing memory and I/O services between nodes
INTEL CORP0 citations62
US12405904B2Sep 2, 2025
Sharing memory and I/O services between nodes
INTEL CORP0 citations62
US7596653B2Sep 29, 2009
Technique for broadcasting messages on a point-to-point interconnect
INTEL CORP2 citations62
US8347018B2Jan 1, 2013
Techniques for broadcasting messages on a point-to-point interconnect
INTEL CORP0 citations52
US7185127B2Feb 27, 2007
Method and an apparatus to efficiently handle read completions that satisfy a read request
INTEL CORP0 citations47