Inventor
SHIH SHING-YIH
TW164 patents
⚠️ This page may combine multiple inventors who share the name “SHIH SHING-YIH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
NANYA TECHNOLOGY CORP
27 patentsUS10181401B1Jan 15, 2019
Method for manufacturing a semiconductor device
NANYA TECHNOLOGY CORP12 citations84
US6821872B1Nov 23, 2004
Method of making a bit line contact device
NANYA TECHNOLOGY CORP19 citations83
US10395976B1Aug 27, 2019
Method of manufacturing semiconductor device
NANYA TECHNOLOGY CORP9 citations82
US10147608B1Dec 4, 2018
Method for preparing a patterned target layer
NANYA TECHNOLOGY CORP8 citations82
US7154159B2Dec 26, 2006
Trench isolation structure and method of forming the same
NANYA TECHNOLOGY CORP12 citations82
US12354965B2Jul 8, 2025
Semiconductor device with redistribution structure and method for fabricating the same
NANYA TECHNOLOGY CORP3 citations75
US12278190B2Apr 15, 2025
Manufacturing method of semiconductor package structure having interconnections between dies
NANYA TECHNOLOGY CORP2 citations75
US12272651B2Apr 8, 2025
Semiconductor package structure having interconnections between dies and manufacturing method thereof
NANYA TECHNOLOGY CORP2 citations75
US12100634B2Sep 24, 2024
Semiconductor device with re-fill layer
NANYA TECHNOLOGY CORP4 citations75
US11315869B1Apr 26, 2022
Semiconductor device with decoupling unit and method for fabricating the same
NANYA TECHNOLOGY CORP6 citations75
US11728316B2Aug 15, 2023
Method for fabricating semiconductor device with heat dissipation features
NANYA TECHNOLOGY CORP2 citations73
US11646292B2May 9, 2023
Method for fabricating semiconductor device with re-fill layer
NANYA TECHNOLOGY CORP2 citations73
US11587901B2Feb 21, 2023
Semiconductor device with redistribution structure and method for fabricating the same
NANYA TECHNOLOGY CORP2 citations73
US11574891B2Feb 7, 2023
Semiconductor device with heat dissipation unit and method for fabricating the same
NANYA TECHNOLOGY CORP2 citations73
US11476200B2Oct 18, 2022
Semiconductor package structure having stacked die structure
NANYA TECHNOLOGY CORP3 citations73
US11462453B2Oct 4, 2022
Semiconductor device with protection layers and method for fabricating the same
NANYA TECHNOLOGY CORP2 citations73
US11355464B2Jun 7, 2022
Semiconductor device structure with bottle-shaped through silicon via and method for forming the same
NANYA TECHNOLOGY CORP4 citations73
US11315904B2Apr 26, 2022
Semiconductor assembly and method of manufacturing the same
NANYA TECHNOLOGY CORP4 citations73
US11302608B2Apr 12, 2022
Semiconductor device with protection layers and method for fabricating the same
NANYA TECHNOLOGY CORP3 citations73
US11211287B2Dec 28, 2021
Semiconductor device and method for fabricating the same
NANYA TECHNOLOGY CORP2 citations73
US11195823B2Dec 7, 2021
Semiconductor package and manufacturing method thereof
NANYA TECHNOLOGY CORP4 citations73
US11177194B2Nov 16, 2021
Semiconductor device with interconnect structure and method for preparing the same
NANYA TECHNOLOGY CORP2 citations73
US11127628B1Sep 21, 2021
Semiconductor device with connecting structure having a step-shaped conductive feature and method for fabricating the same
NANYA TECHNOLOGY CORP4 citations73
US11127632B1Sep 21, 2021
Semiconductor device with conductive protrusions and method for fabricating the same
NANYA TECHNOLOGY CORP6 citations73
US11094662B1Aug 17, 2021
Semiconductor assembly and method of manufacturing the same
NANYA TECHNOLOGY CORP5 citations73
US11063012B1Jul 13, 2021
Semiconductor structure having buffer under bump pad and manufacturing method thereof
NANYA TECHNOLOGY CORP5 citations73
US11043469B1Jun 22, 2021
Method of forming three dimensional semiconductor structure
NANYA TECHNOLOGY CORP2 citations73
MICRON TECHNOLOGY INC
15 patentsUS9786586B1Oct 10, 2017
Semiconductor package and fabrication method thereof
MICRON TECHNOLOGY INC58 citations98
US10937749B2Mar 2, 2021
Methods of forming microelectronic devices including dummy dice
MICRON TECHNOLOGY INC12 citations94
US10872852B2Dec 22, 2020
Wafer level package utilizing molded interposer
MICRON TECHNOLOGY INC20 citations94
US10833052B2Nov 10, 2020
Microelectronic package utilizing embedded bridge through-silicon-via interconnect component and related methods
MICRON TECHNOLOGY INC38 citations94
US10043769B2Aug 7, 2018
Semiconductor devices including dummy chips
MICRON TECHNOLOGY INC17 citations94
US9922845B1Mar 20, 2018
Semiconductor package and fabrication method thereof
MICRON TECHNOLOGY INC44 citations94
US9761559B1Sep 12, 2017
Semiconductor package and fabrication method thereof
MICRON TECHNOLOGY INC39 citations94
US10566229B2Feb 18, 2020
Microelectronic package structures including redistribution layers
MICRON TECHNOLOGY INC6 citations84
US10008461B2Jun 26, 2018
Semiconductor structure having a patterned surface structure and semiconductor chips including such structures
MICRON TECHNOLOGY INC5 citations84
US9922924B1Mar 20, 2018
Interposer and semiconductor package
MICRON TECHNOLOGY INC15 citations84
US9761540B2Sep 12, 2017
Wafer level package and fabrication method thereof
MICRON TECHNOLOGY INC10 citations84
US9721923B1Aug 1, 2017
Semiconductor package with multiple coplanar interposers
MICRON TECHNOLOGY INC13 citations84
US9704790B1Jul 11, 2017
Method of fabricating a wafer level package
MICRON TECHNOLOGY INC13 citations84
US11710693B2Jul 25, 2023
Wafer level package utilizing molded interposer
MICRON TECHNOLOGY INC3 citations73
US10950564B2Mar 16, 2021
Methods of forming microelectronic devices having a patterned surface structure
MICRON TECHNOLOGY INC2 citations73
INOTERA MEMORIES INC
7 patentsUS9607967B1Mar 28, 2017
Multi-chip semiconductor package with via components and method for manufacturing the same
INOTERA MEMORIES INC137 citations98
US9520333B1Dec 13, 2016
Wafer level package and fabrication method thereof
INOTERA MEMORIES INC28 citations94
US9449953B1Sep 20, 2016
Package-on-package assembly and method for manufacturing the same
INOTERA MEMORIES INC46 citations94
US9570369B1Feb 14, 2017
Semiconductor package with sidewall-protected RDL interposer and fabrication method thereof
INOTERA MEMORIES INC17 citations93
US9576931B1Feb 21, 2017
Method for fabricating wafer level package
INOTERA MEMORIES INC8 citations84
US9449935B1Sep 20, 2016
Wafer level package and fabrication method thereof
INOTERA MEMORIES INC11 citations84
US9437583B1Sep 6, 2016
Package-on-package assembly and method for manufacturing the same
INOTERA MEMORIES INC18 citations84
SHIH SHING-YIH
1 patentShowing the top 50 of 164 patents by PatentIndex Score.