Inventor

HOFMANN RICHARD GERARD

US63 patents

⚠️ This page may combine multiple inventors who share the name “HOFMANN RICHARD GERARD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOFMANN RICHARD GERARD

IBM

System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture

Dynamic data bus allocation

Dual burst latency timers for overlapped read and write data transfers

Multi-master computer system with overlapped read and write operations and scalable address pipelining

Processor local bus posted DMA FlyBy burst transfers

Reducing power in a snooping cache based multiprocessor environment

N-way psuedo cross-bar having an arbitration feature using discrete processor local busses

Method and system for optimizing data transfers between devices interconnected by buses operating at different clocking speeds

Method and system for efficiently generating parameterized bus transactions

Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target

System on a chip bus with automatic pipeline stage insertion for timing closure

Multiple frequency communications

Ensuring orderly forward progress in granting snoop castout requests

Methods, arbiters, and computer program products that can improve the performance of a pipelined dual bus data processing system

Speculative direct memory access transfer between slave devices and memory

System and method for providing improved bus utilization via target directed completion

Method for moving snoop pushes to the front of a request queue

Overlapped DMA line transfers

Scalable on-chip bus performance monitoring synchronization mechanism and method of use

Multiprocessor environment supporting variable-sized coherency transactions

Dynamic cache coherency snooper presence with variable snoop latency

QUALCOMM INC

Bus access arbitration scheme

Efficient execution of memory barrier bus commands with order constrained memory accesses

Device directed memory barriers

Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system

Apparatus and methods for weighted bus arbitration among a plurality of master devices based on transfer direction and/or consumed bandwidth

Scalable bus structure

Processing data stream modification to reduce power effects during parallel processing

Processing data stream modification to reduce power effects during parallel processing

Single bus command having transfer information for transferring data in a processing system

Method and apparatus for allocating bandwidth on a transmit channel of a bus

Weakly ordered processing systems and methods

Ticket based request flow control

Bit inversion for data transmission

Enhanced dynamic memory management with intelligent current/power consumption minimization

Enhanced dynamic memory management with intelligent current/power consumption minimization

HOFMANN RICHARD GERARD

Apparatus and methods employing variable clock gating hysteresis for a communications port

Method of associating groups of classified source addresses with vibration patterns

Method and apparatus for adaptive voltage scaling based on instruction usage

Enforcing strongly-ordered requests in a weakly-ordered processing

Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods

Cooperative writes over the address channel of a bus

Cooperative writes over the address channel of a bus

SHIRLEN MARTYN RYAN

Method and apparatus for detecting unauthorized access to a computing device and securely communicating information about such unauthorized access

Method for securely communicating information about the location of a compromised computing device

Memory controllers, systems and methods for applying page management policies based on stream transaction information

Methods and apparatus for resource sharing in a programmable interrupt controller

HANSQUINE DAVID W

Temperature compensating adaptive voltage scalers (AVSs), systems, and methods

ASAAD SAMEH W

System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture

MICROSOFT TECHNOLOGY LICENSING LLC

Providing media power telemetry for virtual machines (VMs) in processor-based devices