Inventor
LAFAUCI PETER DEAN
US9 patents
Patents
9 patentsUS6587905B1Jul 1, 2003
Dynamic data bus allocation
IBM71 citations95
US6513089B1Jan 28, 2003
Dual burst latency timers for overlapped read and write data transfers
IBM57 citations95
US6772254B2Aug 3, 2004
Multi-master computer system with overlapped read and write operations and scalable address pipelining
IBM57 citations94
US6970816B1Nov 29, 2005
Method and system for efficiently generating parameterized bus transactions
IBM20 citations88
US6829731B1Dec 7, 2004
Method and system for generating a design-specific test case from a generalized set of bus transactions
IBM29 citations88
US6718521B1Apr 6, 2004
Method and system for measuring and reporting test coverage of logic designs
IBM30 citations85
US6507808B1Jan 14, 2003
Hardware logic verification data transfer checking apparatus and method therefor
IBM19 citations83
US6430641B1Aug 6, 2002
Methods, arbiters, and computer program products that can improve the performance of a pipelined dual bus data processing system
IBM17 citations83
US6684277B2Jan 27, 2004
Bus transaction verification method
IBM2 citations54