Inventor
NI CHENG-TSUNG
TW13 patents
Patents
13 patentsUS5972754AOct 26, 1999
Method for fabricating MOSFET having increased effective gate length
MOSEL VITELIC INC45 citations96
US6008106ADec 28, 1999
Micro-trench oxidation by using rough oxide mask for field isolation
MOSEL VITELIC INC88 citations94
US6563166B1May 13, 2003
Flash cell device
MOSEL VITELIC INC21 citations92
US6127699AOct 3, 2000
Method for fabricating MOSFET having increased effective gate length
MOSEL VITELIC INC36 citations92
US6284578B1Sep 4, 2001
MOS transistors having dual gates and self-aligned interconnect contact windows
MOSEL VITELIC INC16 citations83
US6228729B1May 8, 2001
MOS transistors having raised source and drain and interconnects
MOSEL VITELIC INC16 citations83
US6821913B2Nov 23, 2004
Method for forming dual oxide layers at bottom of trench
MOSEL VITELIC INC12 citations73
US6150244ANov 21, 2000
Method for fabricating MOS transistor having raised source and drain
MOSEL VITELIC INC7 citations73
US6888197B2May 3, 2005
Power metal oxide semiconductor field effect transistor layout
MOSEL VITELIC INC8 citations72
US6784115B1Aug 31, 2004
Method of simultaneously implementing differential gate oxide thickness using fluorine bearing impurities
MOSEL VITELIC INC7 citations69
US6660592B2Dec 9, 2003
Fabricating a DMOS transistor
MOSEL VITELIC INC3 citations62
US6657263B2Dec 2, 2003
MOS transistors having dual gates and self-aligned interconnect contact windows
MOSEL VITELIC INC5 citations62
US5804493ASep 8, 1998
Method for preventing substrate damage during semiconductor fabrication
MOSEL VITELIC INC6 citations57