Inventor

LAVELLE MICHAEL G

US70 patents

⚠️ This page may combine multiple inventors who share the name “LAVELLE MICHAEL G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAVELLE MICHAEL G

SUN MICROSYSTEMS INC

Scene synchronization of multiple computer displays

Multipurpose memory system for use in a graphics system

Flexible dram access in a frame buffer memory and system

Video frame synchronization of independent timing generators for frame buffers in a master-slave configuration

Interface controller for frame buffer random access memory devices

Programmable sample filtering for image rendering

Efficient method for storing texture maps in multi-bank memory

System and method for computing filtered shadow estimates using reduced bandwidth

Dynamically adjusting sample density in a graphics system

System and method for prefetching data from a frame buffer

Rasterization using two-dimensional tiles and alternating bins for improved rendering utilization

Graphics system configured to switch between multiple sample buffer contexts

Dirty tag bits for 3D-RAM SRAM

Frame buffer memory with on-chip AIU and pixel cache

Graphics system with multiported pixel buffers for accelerated pixel processing

Mechanism for coalescing non-cacheable stores

Frame buffer addressing scheme

Graphics system having a super-sampled sample buffer and having single sample per pixel support

Video frame signature capture

Vertex assembly buffer and primitive launch buffer

Efficient anti-aliased dot rasterization

Synchronizing multiple display channels

Graphics system having a super-sampled sample buffer and having single sample per pixel support

Sample replication mode with depth value calculation

Active block write-back from SRAM cache to DRAM

Dynamically adjusting a number of rendering passes in a graphics system

System and method for handling display device requests for display data from a frame buffer

External dirty tag bits for 3D-RAM SRAM

Reconfigurable hardware filter for texture mapping and image processing

Panning while displaying a portion of the frame buffer image

Batch processing of primitives for use with a texture accumulation buffer

End point value correction when traversing an edge using a quantized slope value

System and method for performing scale and bias operations by preclamping input image data

Parallel read with source-clear operation

Mapping time-sorted to direction-sorted triangle vertices

Multi-channel, demand-driven display controller

Graphics primitive size estimation and subdivision for use with a texture accumulation buffer

Magnified texture-mapped pixel performance in a single-pixel pipeline

Z-slope test to optimize sample throughput

Graphics data synchronization with multiple data paths in a graphics accelerator

Frame buffer organization and reordering

Method and apparatus for reducing inefficiencies in shared memory devices

Splitting grouped writes to different memory blocks

DEERING MICHAEL F

Scalable high performance 3D graphics

Scalable high performance 3D graphics

SILICON IMAGE INC

Method and system for transmitting N-bit video data over a serial link

Method and apparatus for content protection within an open architecture system

MOTOROLA COMPUTER SYSTEMS INC

Video memory controller

Video update FIFO buffer

LAVELLE MICHAEL G

Method and system for transmitting or receiving N-bit video data over a serial link