Inventor

QURESHI QADEER A

US32 patents

⚠️ This page may combine multiple inventors who share the name “QURESHI QADEER A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

QURESHI QADEER A

ADVANCED MICRO DEVICES INC

Method and system for improved memory access in accelerated graphics port systems

Method and system for improved data access

Method and system for page-state sensitive memory control and access in data processing systems

Method and system for improved data transmission in accelerated graphics port systems

Method and system for origin-sensitive memory control and access in data processing systems

Substantially undetectable data processing

Apparatus and method for storing interrupt source information in an interrupt controller based upon interrupt priority

Serial bus for transmitting interrupt information in a multiprocessing system

System and method for validating interrupts before presentation to a CPU

System and method for referencing interrupt request information in a programmable interrupt controller

Method and system for memory control and access in data processing systems

Method and system for destination-sensitive memory control and access in data processing systems

Method and system for generating and utilizing speculative memory access requests in data processing systems

System and method for using random access memory in a programmable interrupt controller

Fail-safe method to read a timer which is based on a particular clock with another asynchronous circit

FREESCALE SEMICONDUCTOR INC

Dynamic voltage adjustment for memory

Temperature based DRAM refresh

Temperature based DRAM refresh

Apparatus and method for adjusting an operating parameter of an integrated circuit

Integrated circuit power management for reducing leakage current in circuit arrays and method therefor

Content addressable memory with search line test circuitry

Nonvolatile memory system using magneto-resistive random access memory (MRAM)

Integrated circuit fuses having corresponding storage circuitry

Memory with fault tolerant reference circuitry

TEXAS INSTRUMENTS INC

System management mode circuits, systems and methods

Method and apparatus for handling system management interrupts (SMI) as well as, ordinary interrupts of peripherals such as PCMCIA cards

Interrupt routing circuits, systems and methods

Integrated circuit design for handling of system management interrupts (SMI)

Buffer memory for I/O writes programmable selective

Frequency independent PCMCIA control signal timing

SPRUTH HENNING F

Hardware-based memory initialization

Memories having a built-in self-test (BIST) feature